Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm
Introduction
Continuous downscaling of silicon devices has fueled an unprecedented growth of integrated circuit complexity and performance, and in turn substantial gains of the semiconductor industry. This traditional geometrical scaling, however, is compromised by shortcomings of the well-known gate stack materials silicon dioxide (SiO2) as dielectric and polysilicon as electrode material. Further reduction of SiO2 thickness is accompanied by an exponential increase of direct gate tunneling leakage currents and future use of polysilicon gate electrodes is limited by a loss of gate capacitance due to polysilicon depletion [1]. Both, high performance as well as low standby power applications are affected by these restrictions. Beginning of “material limited device scaling” is therefore announced by the latest ITRS. Most urgent issue to overcome the fundamental problems is the introduction of new gate stacks, consisting of new dielectric materials with dielectric constants higher (high-k) than SiO2 in combination with metal gate electrodes [2].
Amorphous high-k dielectrics e.g. hafnium- and zirconium-based oxides have been investigated extensively. A low permittivity interfacial layer inherent with these materials, however, limits the achievable maximum gate capacitance and minimum equivalent oxide thickness (EOT) [2]. Epitaxial rare earth oxides, on the other hand, have shown potential to replace SiO2 or oxynitrides for end-of-roadmap complementary metal oxide semiconductor (CMOS) technology [3], [4]. These epitaxial oxides, if deposited by molecular beam epitaxy (MBE), allow abrupt interfaces to silicon substrates and potentially offer perfect lattice matching. Introduction of metal gate electrodes will solve the problem of polysilicon depletion and gate stacks will benefit from an immediate decrease in EOT by several angstroms. A suitable material, however, has to meet several tight boundary conditions such as thermal and chemical stability with the high-k dielectric, work function, suitable interface charge passivation, plasma damage due to reactive ion etching or material deposition and cross contamination issues. Fully silicided (FUSI) nickel silicide (NiSi) metal gates are receiving increased attention for their general CMOS process compatibility and their potential for tuning their work functions [5], [6].
In this paper, we report on experimental results of MOS capacitors with the novel material combination of crystalline Gd2O3 high-k dielectrics and FUSI NiSi metal gate electrodes.
Section snippets
Experimental
Epitaxial Gd2O3 layers of physical thicknesses tox=3.1 nm and 5.9 nm have been grown on 6″ silicon (0 0 1) wafers in a multi-chamber MBE system using granular Gd2O3 [7], [8]. Layers have been covered in vacuo with an amorphous silicon layer. NiSi gate electrodes have been fabricated by forming sputtered nickel dots with a lift-off technique. Full silicidation of the amorphous silicon layer has been achieved by a rapid thermal process at 500 °C in an inert ambient. For an experimental split, part of
Results and discussion
CV characteristics of MOS capacitors with tox=5.9 nm epitaxial Gd2O3 and NiSi electrodes are shown in Fig. 2 (p-type substrate). Nearly identical CV characteristics can be observed for MOS capacitors silicided with and without TiN capping. The maximum capacitance in accumulation of Cmax=2.4 nF yields a capacitance electrical thickness of CET=1.8 nm, which is equal to the 2009 ITRS target for low standby power applications [2]. A dielectric constant of k=13 has been calculated from this CET value.
Conclusion
Epitaxial Gd2O3 high-k dielectrics with CMOS compatible FUSI NiSi metal gate electrodes are investigated in this work. Ultra-low leakage current densities of down to 10−7 A cm−2 are feasible at a capacitance equivalent oxide thickness of CET=1.8 nm, easily meeting the ITRS low stand by power targets for 2009. A TiN capping layer during FUSI silicidation results in improved statistical leakage current variations compared to conventional processing. Ultra-thin Gd2O3 layers of tox=3.1 nm and a CET=0.86
Acknowledgment
The authors wish to express their gratitude to M. Czernohorsky, A. Fissel and H.J. Osten for extensive MBE growth. The authors further gratefully acknowledge financial support by the German Federal Ministry of Education and Research (BMBF) under contract number 01M3142A (“KrisMOS”), AMD Saxony LLC & Co. KG, Infineon Technologies AG, Freescale Halbleiter Deutschland GmbH, and Qimonda AG.
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