CMOS integration of epitaxial Gd2O3 high-k gate dielectrics

doi:10.1016/j.sse.2006.04.018

Solid-State Electronics

Volume 50, Issue 6, June 2006, Pages 979-985

https://doi.org/10.1016/j.sse.2006.04.018 Get rights and content

Abstract

Epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.

Introduction

Scaling of complementary metal oxide semiconductor (CMOS) technology has led to ever increasing complexity and performance of electronic applications [1]. In the near future, however, further scaling will require new dielectric materials and metal electrodes to meet the targets of the International Technology Roadmap for Semiconductors (ITRS) for gate leakage currents and equivalent oxide thickness [2].

While hafnium-based oxides are widely studied as the alleged high-k material of choice, their introduction into manufacturing has been postponed repeatedly due to shortcomings in device performance. Instead, crystalline rare earth oxides have shown potential to replace silicon oxide or oxynitrides for end-of-roadmap CMOS technology [3], [4]. These crystalline oxides, if grown by molecular beam epitaxy (MBE), allow abrupt interfaces to silicon substrates and perfect lattice matching. Any metal gate electrode, while solving the problem of polysilicon depletion, faces a range of tight boundary conditions such as thermal and chemical stability with the high-k dielectric, work function adequacy, interface charge passivation, plasma damage due to reactive ion etching or material deposition or cross contamination issues. Among many choices, titanium nitride and fully silicided (FUSI) nickel silicide metal gates are receiving increased attention for their general CMOS process compatibility and their potential for tuning their work functions [5], [6].

In this work the compatibility of CMOS process steps with epitaxial high-k gadolinium oxide (Gd₂O₃) layers is investigated. The influence of wet chemical cleaning, resist stripping, reactive ion etching (RIE), lithographic steps, and thermal treatments is studied on the basis of MOS structures with Gd₂O₃ dielectrics and polysilicon, TiN and NiSi gate electrodes. A feasible MOSFET process sequence is identified. Finally, ultra-thin body (UTB) silicon on insulator SOI MOSFETs with epitaxial Gd₂O₃ high-k gate dielectrics and TiN metal electrodes are presented for the first time.

Section snippets

Experimental

Crystalline Gd₂O₃ high-k dielectric layers have been grown on (0 0 1) oriented Si by a modified epitaxy process at 600 °C in a DCA Instruments multi-chamber ultrahigh vacuum system [7]. Before insertion into vacuum, p-type (boron) 6 in. Si wafers with a resistivity of 0.01–0.02 Ω cm have been cleaned with RCA-based wet chemical cleaning and diluted HF. In addition, a SOI wafer with a p-type top silicon thickness of t_Si = 20 nm and a buried oxide thickness of t_BOX = 400 nm has been prepared likewise. The

Electrode materials

Polysilicon electrodes have been activated using RTA with various inert ambients at temperatures between 800 °C and 930 °C. All experiments resulted in extremely high leakage currents (not shown) for the n+ polysilicon/Gd₂O₃/p-Si MOS capacitors and CV characteristics could therefore not be obtained. A severe reaction of the gate dielectric with the gate electrode is likely responsible for these results.

NiSi and TiN electrodes, however, have resulted in the measurement of well behaved CV

Conclusion

The compatibility of epitaxial Gd₂O₃ gate dielectrics with typical CMOS process steps has been investigated. Wet chemical cleaning, lithography, resist stripping, and dry etching have been found to be compatible with Gd₂O₃ with the exception of oxidizing steps like H₂O₂:H₂SO₄ baths or oxygen plasmas. The thermal stability of the gate oxide/gate electrode interface strongly depends on the electrode material. Standard polysilicon electrodes with their high temperature activation steps are not

Acknowledgements

The authors acknowledge financial support by the German Federal Ministry of Education and Research (BMBF project “KrisMOS”, 01 M 3142), AMD Saxony LLC & Co. KG, Infineon Technologies AG and Freescale Halbleiter Deutschland GmbH. Furthermore, FIB preparation, TEM, and EDX analysis by M. Bückins, F. Dorn, T. Weirich, and J. Mayer from GFE, RWTH Aachen University, is gratefully acknowledged.

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CMOS integration of epitaxial Gd2O3 high-k gate dielectrics

Abstract

Introduction

Section snippets

Experimental

Electrode materials

Conclusion

Acknowledgements

Solid-State Electron.

Microelectron Eng

Microelectron Eng

Nanoscale CMOS

Proc IEEE

High-k gate dielectrics with ultra-low leakage current based on praseodymium oxide

IEDM Tech Dig

Properties of high-k gate dielectrics Gd2O3 and Y2O3 for Si

J Appl Phys

CMOS integration of epitaxial Gd₂O₃ high-k gate dielectrics

Properties of high-k gate dielectrics Gd₂O₃ and Y₂O₃ for Si