Investigation of thin gate-stack Z2-FET devices as capacitor-less memory cells
Introduction
The traditional 1 transistor – 1 capacitor (1T-1C) DRAM memory cell is approaching its scaling limit [1]. The capacitor can no longer follow the transistor scaling trend since a minimum and technology-independent capacitance is required to guarantee correct memory cell operation [2]. Capacitor-less memory cell architectures, formed solely by one transistor, are a promissing solution for future electronics.
Capacitor-less memory cells are based on the SOI-FET floating body effect [3] by which charge can be stored in the body of the transistor, modulating the threshold voltage and exhibiting distinct drain currents. The body of the memory cell is then fully depleted from or accumulated with carriers to obtain two distinct current levels corresponding to the complementary logic states.
In order to further increase the DRAM integration density limiting the fabrication costs, key aspects for embedded applications, novel capacitor-less cells [4], such as the MSDRAM [5], the A2RAM [6], [7] or the Z2-FET [8] have been proposed. All these cells meet most of the stringent next generation DRAM requirements: work under low voltage, present low power consumption, exhibit long retention times and are scalable. Among all this 1T-DRAM cell candidates, the Z2-FET stands out for its performance and feasible integration with the standard fabrication process in ultra-thin body structures [9], [10], [11].
Recently it was demonstrated the operation of a fully operational 2 × 2 Z2-FET matrix [12] successfully probing simultaneous word programming and reading. In this work, characterization results of 1T-DRAM Z2-FET cells on 28 nm FDSOI [13] with ultra-thin gate oxide are reported. The measured devices were chosen to characterize both the width (W) and the gate length () dependence on the cell operation with a fixed ungated length ( nm), as shown in Table 1. Section 2 explains the Z2-FET structure and operation as memory cell and the sharp current switch mechanism. The 1T-DRAM operation is experimentally verified in Section 3. Section 4 Memory window, 5 Retention time illustrate the memory window and retention time respectively to quantify the memory cell performance. Finally, Section 6 is devoted to the variability characterization of some of these cells.
Section snippets
Device structure
The Z2-FET DRAM cell basic structure is depicted in Fig. 1. It is similar to a conventional PIN diode in which the intrinsic region is partially covered by a front gate (FG); below the whole device, a highly-doped ground-plane (GP) acting as back gate (BG) is implemented.
The Z2-FET cells were characterized both at simulation and experimental level. Synopsys Sentaurus [14] software was used to properly confirm the device principles of operation. A 2D structure following the architecture shown in
DRAM validation
To verify the Z2-FET DRAM operation, both logic states need to be written and then read back. Since the cell transient response depends on the accumulated carriers on the body, electrons are evacuated before the operation or accumulated before the operation to ensure the worst scenario. The pattern is applied to the cell (Fig. 6) where the timing conditions were optimized to reduce the leakage current and RC parasitic discharges in the setup. Since the operation of this cell
Memory window
The memory window indicates the range of anode voltages in which the cell exhibits memory effect for a given timing and gate bias conditions. It is defined as the difference between the two logic states, so the larger it is the more robust the memory cell is against anode reading voltage variability. The memory window is extracted by monitoring the anode current level for different anode reading pulse voltages, see inset in Fig. 9a. The delay between the write and read operations is limited
Retention time
The retention time is characterized with several -H-R bias patterns, as illustrated in the inset of Fig. 10a. The holding (H) time is gradually increased from 20 to 70 ms, to monitor if the previously programmed state () is still available afterwards. Consistent retention times are only reported for and , Fig. 10, since for the remaining devices a different is required, thus a fair comparison is not possible. In contrast with other 1T-DRAM cells [5], [7] where the
DC variability
Statistical measurements of some Z2-FET devices were performed to assess the wafer-level variability. A set of 56 devices were studied for the wafer-level variability at V. The test is based on the DC characteristics which provide the key parameters to be used in the memory operation measurement as shown in Fig. 12. Devices with nm, W = 1 and 0.1 are chosen and compared to evaluate the variability. Fig. 13, Fig. 14 show the spreading of Z2-FET parameters: a) ON voltage, b)
Conclusion
Advanced narrow Z2-FET memory cells with ultrathin gate oxide have been experimentally characterized. Retention times and memory windows have been determined for the first time. The memory operation is successfully demonstrated despite a performance drop with respect to previous results, due to increased variability, vertical electric field and gate leakage.
Acknowledgment
H2020 REMINDER European project (grant agreement No 687931) and TEC2014-59730 are thanked for financial support.
References (14)
- et al.
Experimental developments of A2RAM memory cells on SOI and bulk substrates
Solid-State Electron
(2015) - Semiconductor Industry Association. International Technology Roadmap for Semiconductors (ITRS);...
Recent innovations in DRAM manufacturing
IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC) San Francisco, CA
(2010)Silicon-On-Insulator Technology: Materials of VLSI
(2004)- et al.
A SOI capacitor-less 1T-DRAM concept
- et al.
A capacitorless 1T-DRAM on SOI based on dynamic coupling and double-gate operation
IEEE Electron Device Lett
(2008) - et al.
Experimental demonstration of capacitorless A2RAM cells on silicon-on-insulator
IEEE Electron Device Lett
(Dec. 2012)
Cited by (3)
Dependence of latch-up and threshold voltages on channel length in single-gated feedback field-effect transistor
2022, Semiconductor Science and TechnologyUnderstanding of feedback field-effect transistor and its applications
2020, Applied Sciences (Switzerland)