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BIST Pattern Generators Using Addition and Subtraction Operations

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Abstract

Configurations of adders, subtracters, or arithmetic logic units andregisters, which are available in many data paths, can be utilized togenerate patterns and to compact test responses. This paper analyzesthe pattern sequences generated by configurations with differenttypes of adders and subtracters. For many different seeds andconstant input values, these pattern generators can produce asequence of all possible patterns. Moreover, k-bit patterngenerators that take into account the overflow or underflow bit cangenerate bit sequences that all have period 2k-1. Thus, theperiodicity of these pattern generators is the same as that of a k-bit linear feedback shift register with a primitivecharacteristic polynomial. Experimental results show that theproduced pattern sequences achieve similar fault coverage aspseudorandom sequences and require about the same testlength. Compared to the well-known self-test methods that insert testregisters, the approach using available arithmetic units saves theadditional gates that are needed to implement test registers, and itavoids performance degradation due to additional delays.

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Authors and Affiliations

  1. Institute of Computer Design and Fault Tolerance, University of Karlsruhe, D-76128, Karlsruhe, Germany

    Albrecht P. Stroele

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  1. Albrecht P. Stroele
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Stroele, A.P. BIST Pattern Generators Using Addition and Subtraction Operations. Journal of Electronic Testing 11, 69–80 (1997). https://doi.org/10.1023/A:1008299817888

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