Abstract
This paper addresses the problem of testing the RAM mode of the LUT/RAM modules of configurable SRAM-based Field Programmable Gate Arrays (FPGAs) using a minimum number of test configurations. A model of architecture for the LUT/RAM module with N inputs and 2N memory cells is proposed taking into account the LUT and RAM modes. Targeting the RAM mode, we demonstrate that a unique test configuration is required for a single module. The problem is shown equivalent to the test of a classical SRAM circuit allowing to use existing algorithms such as the March tests. We also propose a unique test configuration called ‘pseudo shift register’ for an m × m array of modules. In the proposed configuration, the circuit operates as a shift register and an adapted version of the MATS++ algorithm called ‘shifted MATS++’ is described.
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References
S.D. Brown, R.J. Francis, J. Rose, and S.G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, 1992.
S.M. Trimberger (Ed.), Field-Programmable Gate Array Technology, Kluwer Academic Publishers, 1994.
M. Renovell, J. Figueras, and Y. Zorian, “Test of RAM-Based FPGA: Methodology and Application to the Interconnect,” Proc. 15th IEEE VLSI Test Symposium, Monterey, CA, USA, May 1997, pp. 230–237.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “Testing the Interconnect of RAM-Based FPGAs,” IEEE Design & Test of Computer, special issue on FPGAs, Vol. 15, No. 1, pp. 45–50, Jan.–March 1998.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “SRAM-Based FPGA': Testing the Interconnect/Logic Interface,” Proc. 7th Asian Test Symposium, Singapore, Dec. 1998, pp. 266–277.
C. Jordan and W.P. Marnane, “Incoming Inspection of FPGAs,” Proc. of IEEE European Test Conference, 1993, pp. 371–377.
T. Inoue, H. Fujiwara, H. Michinishi, T. Yokohira, and T. Okamoto, “Universal Test Complexity of Field-Programmable Gate Arrays,” Proc. 4th Asian Test Symposium, Bangalore, India, Nov. 1995, pp. 259–265.
W.K. Huang and F. Lombardi, “An Approach for Testing Programmable/Configurable Field Programmable Gate Arrays,” Proc. 14th IEEE VLSI Test Symposium, Princeton, NJ, USA, May 1996, pp. 450–455.
M. Abramovici and C. Stroud, “No-Overhead BIST for FPGAs,” Proc. 1st IEEE International On-Line Testing Workshop, Nice, France, 1995, pp. 90–92.
C. Stroud, P. Chen, S. Konala, and M. Abramovici, “Evaluation of FPGA Ressources for Built-In Self Test of Programmable Logic Blocks,” Proc. of 4th ACM/SIGDA Int. Symposium on FPGAs, 1996, pp. 107–113.
M. Abramovici and C. Stroud, “ILA BIST for FPGAs: A Free Lunch with Gourmet Food,” Proc. 2nd IEEE International On-Line Testing Workshop, Biarritz, France, 1996, pp. 91–95.
F. Lombardi, D. Ashen, X.T. Chen, and W.K. Huang, “Diagnosing Programmable Interconnect Systems for FPGAs,” '96, Monterey, CA, USA, 1996, pp. 100–106.
W.K. Huang, F.J. Meyer, N. Park, and F. Lombardi, “Testing Memory Modules in SRAM-Based Configurable FPGAs,” IEEE International Workshop on Memory Technology, Design and Test, Aug. 1997.
M. Hermann and W. Hoffmann, “Fault Modeling and Test Generation for FPGAs,” Lecture Notes in Computer Science, Field Programmable Logic, R.W. Hartenstein and M.Z. Servit (Eds.), Springer-Verlag, 1994, pp. 1–10.
R.O. Durate and M. Nicolaidis, “A Test Methodology Applied to Cellular Logic Programmable Gate Arrays,” Lecture Notes in Computer Science, Field Programmable Logic, R.W. Hartenstein and M.Z. Servit (Eds.), Springer-Verlag, 1994, pp. 11–22.
T. Liu, W.K. Huang, and F. Lombardi, “Testing of Uncustomized Segmented Channel FPGAs,” Proc. of ACM Int. Symp. on FPGAs, 1995, pp. 125–131.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “Test Pattern and Test Generation Methodology for the Logic of RAM-Based FPGA,” Proc. IEEE Asian Test Symposium, Akita, Japan, Nov. 1997, pp. 254–259.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “Testing the Configurable Logic of RAM-Based FPGA,” Proc. IEEE Int. Conf. on Design, Automation and Test in Europe, Paris, France, Feb. 1998, pp. 82–88.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “SRAM-Based FPGA: Testing the LUT/RAM Modules,” Proc. IEEE Int. Test Conf., Washington, DC, USA, Oct. 1998, pp. 1102–1111.
M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian, “SRAM-Based FPGA: A Fault Model for the Configurable Logic Modules,” Proc. 8th Int. Workshop on Field Prog. Logic and Applications, Tallinn, Estonia, Sept. 1998, pp. 139–148.
M.S. Abadir and J.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,” ACM Computing Surveys, Vol. 15, No. 3, pp. 175–198, 1983.
M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Computer Science Press, Inc., Woodland Hills, CA, USA, 1976.
A.J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Willey & Sons, 1991.
J. Knaizuk, Jr. and C.R.P. Hartmann, “An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories,” IEEE Trans. on Computers, Vol. C-26, No. 11, pp. 1141–1144, 1977.
R. Nair, “Comments on: An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories,” IEEE Trans. on Computers, Vol. C-28, No. 3, pp. 258–261, 1979.
M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,” Proc. IEEE Int. Test Conference, 1982, pp. 236–239.
D.S. Suk and S.M. Reddy, “A March Test for Functional Faults in Semiconductor Random-Access Memories,” IEEE Trans. on Computers, Vol. C-30, No. 12, pp. 982–985, 1981.
Xilinx, The Programmable Logic Data Book, San Jose, USA, 1994.
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Renovell, M., Portal, J., Figueras, J. et al. SRAM-Based FPGAs: Testing the Embedded RAM Modules. Journal of Electronic Testing 14, 159–167 (1999). https://doi.org/10.1023/A:1008326111919
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DOI: https://doi.org/10.1023/A:1008326111919