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Deterministic BIST with Multiple Scan Chains

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Abstract

A deterministic BIST scheme for circuits with multiple scan paths is presented. A procedure is described for synthesizing a pattern generator which stimulates all scan chains simultaneously and guarantees complete fault coverage.

The new scheme may require less chip area than a classical LFSR-based approach while better or even complete fault coverage is obtained at the same time.

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Authors and Affiliations

  1. Computer Architecture Lab, Institute of Computer Science, University of Stuttgart, Breitwiesenstr 20/22, 70565, Stuttgart, Germany

    Gundolf Kiefer & Hans-Joachim Wunderlich

Authors
  1. Gundolf Kiefer
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  2. Hans-Joachim Wunderlich
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Kiefer, G., Wunderlich, HJ. Deterministic BIST with Multiple Scan Chains. Journal of Electronic Testing 14, 85–93 (1999). https://doi.org/10.1023/A:1008353423305

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