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Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments

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Abstract

The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviours. This paper discusses alternative approaches to perform transient fault injection in circuits described in a high level language such as VHDL. In the proposed analysis flow, a behavioural model is generated, allowing the designer to identify the detailed error propagation paths in the circuit. This paper also reports on results obtained with SEU-like fault injections in VHDL descriptions of digital circuits. Several circuit description levels are considered, as well as several fault modelling levels. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.

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  1. TIMA Laboratory, Qualification Group, 46, Avenue Félix Viallet, 38031, Grenoble Cedex, France

    R. Leveugle & K. Hadjiat

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  1. R. Leveugle
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  2. K. Hadjiat
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Leveugle, R., Hadjiat, K. Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. Journal of Electronic Testing 19, 559–575 (2003). https://doi.org/10.1023/A:1025178014797

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