Origin of the dielectric dead layer in nanoscale capacitors

Abstract

Capacitors are a mainstay of electronic integrated circuits and devices, where they perform essential functions such as storing electrical charge, and blocking direct current while allowing alternating currents to propagate. Because they are often the largest components in circuits, extensive efforts are directed at reducing their size through the use of high-permittivity insulators such as perovskite-structure SrTiO₃ (refs 1, 2), which should provide more capacitance per unit area of device. Unfortunately, most experiments on thin-film SrTiO₃ capacitors have yielded capacitance values that are orders of magnitude smaller than expected³. The microscopic origin of this reduced capacitance, which is often discussed in terms of a low-permittivity interfacial ‘dead layer’⁴, is not well understood. Whether such a dead layer exists at all, and if so, whether it is an intrinsic property of an ideal metal–insulator interface or a result of processing issues such as defects and strains, are controversial questions. Here we present fully ab initio calculations of the dielectric properties of realistic SrRuO₃/SrTiO₃/SrRuO₃ nanocapacitors, and show that the observed dramatic capacitance reduction is indeed an intrinsic effect. We demonstrate the existence of a dielectric dead layer by calculating the dielectric profile across the interface and analyse its origin by extracting the ionic and electronic contributions to the electrostatic screening. We establish a correspondence between the dead layer and the hardening of the collective SrTiO₃ zone-centre polar modes, and determine the influence of the electrode by repeating our calculations for Pt/SrTiO₃/Pt capacitors. Our results provide practical guidelines for minimizing the deleterious effects of the dielectric dead layer in nanoscale devices.