High-speed graphene transistors with a self-aligned nanowire gate

Abstract

Graphene has attracted considerable interest as a potential new electronic material^{1,2,3,4,5,6,7,8,9,10,11}. With its high carrier mobility, graphene is of particular interest for ultrahigh-speed radio-frequency electronics^{12,13,14,15,16,17,18}. However, conventional device fabrication processes cannot readily be applied to produce high-speed graphene transistors because they often introduce significant defects into the monolayer of carbon lattices and severely degrade the device performance^19,20,21. Here we report an approach to the fabrication of high-speed graphene transistors with a self-aligned nanowire gate to prevent such degradation. A Co₂Si–Al₂O₃ core–shell nanowire is used as the gate, with the source and drain electrodes defined through a self-alignment process and the channel length defined by the nanowire diameter. The physical assembly of the nanowire gate preserves the high carrier mobility in graphene, and the self-alignment process ensures that the edges of the source, drain and gate electrodes are automatically and precisely positioned so that no overlapping or significant gaps exist between these electrodes, thus minimizing access resistance. It therefore allows for transistor performance not previously possible. Graphene transistors with a channel length as low as 140 nm have been fabricated with the highest scaled on-current (3.32 mA μm⁻¹) and transconductance (1.27 mS μm⁻¹) reported so far. Significantly, on-chip microwave measurements demonstrate that the self-aligned devices have a high intrinsic cut-off (transit) frequency of f_T = 100–300 GHz, with the extrinsic f_T (in the range of a few gigahertz) largely limited by parasitic pad capacitance. The reported intrinsic f_T of the graphene transistors is comparable to that of the very best high-electron-mobility transistors with similar gate lengths¹⁰.