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Academic and industry research progress in germanium nanodevices

Nature volume 479, pages 324–328 (2011)Cite this article

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Abstract

Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

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Figure 1: The mobility landscape of semiconductors.
Figure 2: The integration of germanium on silicon.
Figure 3: The two main germanium device architectures.
Figure 4: Benchmarking germanium device mobility.
Figure 5: Short-channel performance of p-type non-silicon devices.

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References

  1. Moore, G. E. No exponential is forever: but 'forever' can be delayed! Digest Tech. Papers Int. Solid-State Circuits Conf. 20–23 (IEEE, 2003).

    Google Scholar 

  2. Ghani, T. et al. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. Tech. Digest IEEE Electron Devices Meet. 11.6.1–11.6.3 (IEEE, 2003).

    Google Scholar 

  3. Mistry, K. et al. A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging. Tech. Digest IEEE Electron Devices Meet. 247–250 (IEEE, 2007).

    Google Scholar 

  4. Kim, D. & Del Alamo, J. Scaling behavior of In0.7Ga0.3As HEMTs for logic. Tech. Digest IEEE Electron Devices Meet. 837–841 (IEEE, 2006).

    Google Scholar 

  5. Hudait, M. et al. Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin (< 2 μm) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. Tech. Digest IEEE Electron Devices Meet. 625–628 (IEEE, 2007).

    Google Scholar 

  6. Radosavljevic, M. et al. Advanced high-κ gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications. Tech. Digest IEEE Electron Devices Meet. 319–322 (IEEE, 2009).

    Google Scholar 

  7. Dewey, G. et al. Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (V CC) ranging from 0.5 V to 1.0 V. Tech. Digest IEEE Electron Devices Meet. 487–490 (IEEE, 2009).

    Google Scholar 

  8. Radosavljevic, M. et al. High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (V CC = 0.5 V) logic applications. Tech. Digest IEEE Electron Devices Meet. 727–730 (IEEE, 2008).

    Google Scholar 

  9. Kudo, M., Matsumoto, H., Tanimoto, T., Mishima, T. & Ohbu, I. Improved hole transport properties of highly strained In0.35Ga0.65As channel double-modulation-doped structures grown by MBE on GaAs. J. Cryst. Growth 175, 910–914 (1997).

    Google Scholar 

  10. Nagaiah, P., Tokranov, V. & Oktyabrsky, S. Strained quantum wells for p-channel InGaAs CMOS. Mater. Res. Soc. Symp. Proc. 1108-A12-01 (Cambridge Univ. Press, 2009).

    Google Scholar 

  11. Schirber, J. E., Fritz, I. J. & Dawson, L. R. Light hole conduction in InGaAs/GaAs strained-layer superlattices. Appl. Phys. Lett. 46, 187–189 (1985).

    Article  ADS  CAS  Google Scholar 

  12. Bennett, B. R., Ancona, M. G., Boos, J. B. & Shanabrook, B. V. Mobility enhancement in strained p-InGaSb quantum wells. Appl. Phys. Lett. 91, 042104 (2007).

    Article  ADS  Google Scholar 

  13. Chang, L. L. & Yu, H. N. The germanium insulated-gate-field-effect transistor (FET). Proc. IEEE 5, 316–317 (IEEE, 1965).

    Google Scholar 

  14. Wang, K. L. & Gray, P. V. Fabrication and characterization of germanium ion-implanted IGFET's. IEEE Trans. Electron Devices 22, 353–355 (1975).

    Article  ADS  Google Scholar 

  15. Martin, S. C., Hitt, L. M. & Rosenberg, J. J. p-Channel germanium MOSFET's with high channel mobility. IEEE Electron Device Lett. 10, 325–326 (1989).

    Article  ADS  CAS  Google Scholar 

  16. Lee, M. L. et al. Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−x Ge x /Si virtual substrates. Appl. Phys. Lett. 79, 3344–3346 (2001).

    Article  ADS  CAS  Google Scholar 

  17. Weber, O. et al. Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS. Tech. Digest IEEE Electron Devices Meet. 137–140 (IEEE, 2005).

    Google Scholar 

  18. Krishnamohan, T., Krivokapic, Z., Uchida, K., Nishi, Y. & Saraswat, K. C. Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT). Tech. Digest Papers Symp. VLSI Technol. 82–83 (IEEE, 2005).

    Google Scholar 

  19. Nicholas, G. et al. High mobility strained Ge pMOSFETs with high-κ/metal gate. IEEE Electron Device Lett. 28, 825–827 (2007).

    Article  ADS  CAS  Google Scholar 

  20. Ni Chleirigh, C. Strained SiGe-channel p-MOSFETs: Impact of Heterostructure Design and Process Technology. PhD thesis, Mass. Inst. Technol. (2007).

    Google Scholar 

  21. Mitard, J. et al. Record I ON/I OFF performance for 65 nm Ge pMOSFET and novel Si passivation scheme for improved EOT scalability. Tech. Digest IEEE Electron Devices Meet. 873–876 (IEEE, 2008). This article reports on state-of-the-art short-channel germanium MOSFET performance.

    Google Scholar 

  22. Mitard, J. et al. Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI. Tech. Digest Papers Symp. VLSI Technol. 82–83 (IEEE, 2009).

    Google Scholar 

  23. Gomez, L., Ni Chleirigh, C., Hashemi, P. & Hoyt, J. L. Enhanced hole mobility in high Ge content asymmetrically strained-SiGe p-MOSFETs. IEEE Electron Device Lett. 31, 782–784 (2010). This article reports the highest mobility achieved so far in a germanium QWFET.

    Article  ADS  CAS  Google Scholar 

  24. Pillarisetty, R. et al. High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (V CC = 0.5 V) III–V CMOS architecture. Tech. Digest IEEE Electron Devices Meet. 150–153 (IEEE, 2010). This article describes state-of-the-art mobility and short-channel performance in a germanium QWFET with a scaled TOXE.

    Google Scholar 

  25. Chui, C. et al. A sub-400 °C germanium MOSFET technology with high-κ dielectric and metal gate. Tech. Digest IEEE Electron Devices Meet. 437–440 (IEEE, 2002).

    Book  Google Scholar 

  26. Huang, C. H. et al. Very low defects and high performance Ge-on-insulator p-MOSFETs with Al2O3 gate dielectrics. Tech. Digest Papers Symp. VLSI Technol. 119–120 (IEEE, 2003).

    Google Scholar 

  27. Ritenour, A. et al. Epitaxial strained germanium p-MOSFETs with HfO2 gate dielectric and TaN gate electrode. Tech. Digest IEEE Electron Devices Meet. 433–436 (IEEE, 2003).

    Google Scholar 

  28. Whang, S. J. et al. Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AIN) and TaN/HfO2 gate stack. Tech. Digest IEEE Electron Devices Meet. 307–310 (IEEE, 2004).

    Google Scholar 

  29. Kuzum, D. et al. Interface-engineered Ge (100) and (111), N- and P-FETs with high mobility. Tech. Digest IEEE Electron Devices Meet. 723–726 (IEEE, 2007).

    Google Scholar 

  30. Kita, K. et al. Comprehensive study of GeO2 oxidation, GeO desorption and GeO2–metal interaction: understanding of Ge processing kinetics for perfect interface control. Tech. Digest IEEE Electron Devices Meet. 693–696 (IEEE, 2009).

    Google Scholar 

  31. Wang, S. K. et al. Desorption kinetics of GeO from GeO2/Ge structure. J. Appl. Phys. 108, 054104 (2010).

    Article  ADS  Google Scholar 

  32. Tezuka, T. et al. A new strained-SOI/GOI dual CMOS technology based on local condensation technique. Tech. Digest Papers Symp. VLSI Technol. 80–81 (IEEE, 2005).

    Google Scholar 

  33. Zhang, R., Iwasaki, T., Taoka, N., Takenaka, M. & Takagi, S. High mobility Ge pMOSFETs with ∼ 1 nm thin EOT using Al2O3/GeO x /Ge gate stacks fabricated by plasma post oxidation. Tech. Digest Papers Symp. VLSI Technol. 56–57 (IEEE, 2011). This article describes state-of-the-art mobility in a germanium MOSFET with a scaled TOXE.

    Google Scholar 

  34. Xu, H. X., Xu, J. P., Li, C. X. & Lai, P. T. Improved electrical properties of Ge metal–oxide–semiconductor capacitors with high-κ HfO2 gate dielectric by using La2O3 interlayer sputtered with/without N2 ambient. Appl. Phys. Lett. 97, 022903 (2010).

    Article  ADS  Google Scholar 

  35. Swaminathan, S., Shandalov, M., Oshima, Y. & McIntyre, P. C. Bilayer metal oxide gate insulators for scaled Ge-channel metal–oxide–semiconductor devices. Appl. Phys. Lett. 96, 082904 (2010).

    Article  ADS  Google Scholar 

  36. Caymax, M. et al. Germanium for advanced CMOS anno 2009: a SWOT analysis. Tech. Digest IEEE Electron Devices Meet. 461–464 (IEEE, 2009).

    Google Scholar 

  37. Kamata, Y. High-k/Ge MOSFETs for future nanoelectronics. Mater. Today 11, 30–38 (2008).

    Article  Google Scholar 

  38. Xie, Y. H. et al. Very high mobility two-dimensional hole gas in Si/Ge x Si1−x /Ge structures grown by molecular beam epitaxy. Appl. Phys. Lett. 63, 2263–2264 (1993).

    Article  ADS  CAS  Google Scholar 

  39. Engelhardt, C. M. et al. High mobility 2-D hole gases in strained Ge channels on Si substrates studied by magnetotransport and cyclotron resonance. Solid State Electron. 37, 949–952 (1994).

    Article  ADS  CAS  Google Scholar 

  40. Madhavi, S., Venkataraman, V. & Xie, Y. H. High room temperature hole mobility in Ge0.7Si0.3/Ge/Ge0.7Si0.3 modulation doped heterostructures in the absence of parallel conduction. J. Appl. Phys. 89, 2497–2499 (2001).

    Article  ADS  CAS  Google Scholar 

  41. Irisawa, T., Miura, H., Ueno, T. & Shiraki, Y. Channel width dependence of mobility in Ge channel modulation doped structures. Jpn. J. Appl. Phys. 40, 2694–2696 (2001).

    Article  ADS  CAS  Google Scholar 

  42. Koester, S. J., Hammond, R. & Chu, J. O. Extremely high transconductance Ge/Si0.4Ge0.6 p-MODFET's grown by UHV-CVD. IEEE Electron Device Lett. 21, 110–112 (2000).

    Google Scholar 

  43. Houssa, M. et al. Ge dangling bonds at the (100)Ge/GeO2 interface and the viscoelastic properties of GeO2 . Appl. Phys. Lett. 93, 161909 (2008).

    Article  ADS  Google Scholar 

  44. Atalla, M. M., Tannenbaum, E. & Scheibner, E. J. Stabilization of silicon surfaces by thermally grown oxides. Bell Syst. Tech. J. 38, 749–783 (1959).

    Article  Google Scholar 

  45. Kahng, D. Silicon–silicon dioxide surface devices. Technical memorandum (Bell Laboratories, 16 January 1961); reprinted in Sze, S. M. (ed.) Semiconductor Devices: Pioneering Papers 583–596 (World Scientific Publishing, 1991).

    Book  Google Scholar 

  46. Currie, M. T., Samavedam, S. B., Langdo, T. A., Leitz, C. W. & Fitzgerald, E. A. Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical–mechanical polishing. Appl. Phys. Lett. 72, 1718–1720 (1998).

    Article  ADS  CAS  Google Scholar 

  47. Park, J. S. et al. Defect reduction of selective Ge epitaxy in trenches on Si (001) substrates using aspect ratio trapping. Appl. Phys. Lett. 90, 052113 (2007).

    Article  ADS  Google Scholar 

  48. Wang, G. et al. Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches. Thin Solid Films 518, 2538–2541 (2010).

    Article  ADS  CAS  Google Scholar 

  49. Wang, G. et al. High quality Ge epitaxial layers in narrow channels on Si (001) substrates. Appl. Phys. Lett. 96, 111903 (2010).

    Article  ADS  Google Scholar 

  50. Taraschi, G., Pitera, A. J. & Fitzgerald, E. A. Strained Si, SiGe, and Ge on-insulator: review of wafer bonding fabrication techniques. Solid State Electron. 47, 1297–1305 (2004).

    Article  ADS  Google Scholar 

  51. Nakaharai, S., Tezuka, T., Sugiyama, N., Moriyama, Y. & and Takagi, S. Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique. Appl. Phys. Lett. 83, 3516–3518 (2003).

    Article  ADS  CAS  Google Scholar 

  52. Hashimoto, T., Yoshimoto, C., Hosoi, T., Shimura, T. & Watanabe, H. Fabrication of local Ge-on-insulator structures by lateral liquid-phase epitaxy: effect of controlling interface energy between Ge and insulators on lateral epitaxial growth. Appl. Phys. Express 2, 066502 (2009).

    Article  ADS  Google Scholar 

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  1. Components Research, Technology and Manufacturing Group, Intel Corporation, 5200 Northeast Elam Young Parkway, Hillsboro, 97124, Oregon, USA

    Ravi Pillarisetty

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Correspondence to Ravi Pillarisetty.

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Pillarisetty, R. Academic and industry research progress in germanium nanodevices. Nature 479, 324–328 (2011). https://doi.org/10.1038/nature10678

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