SCHEDULED MAINTENANCE
High-performance sub-10 nm monolayer Bi2O2Se transistors†
Abstract
A successful two-dimensional (2D) semiconductor successor of silicon for high-performance logic in the post-silicon era should have both excellent performance and air stability. However, air-stable 2D semiconductors with high performance were quite elusive until the air-stable Bi2O2Se with high electron mobility was fabricated very recently (J. Wu, H. Yuan, M. Meng, C. Chen, Y. Sun, Z. Chen, W. Dang, C. Tan, Y. Liu, J. Yin, Y. Zhou, S. Huang, H. Q. Xu, Y. Cui, H. Y. Hwang, Z. Liu, Y. Chen, B. Yan and H. Peng, Nat. Nanotechnol., 2017, 12, 530). Herein, we predict the performance limit of the monolayer (ML) Bi2O2Se metal oxide semiconductor field-effect transistors (MOSFETs) by using ab initio quantum transport simulation at the sub-10 nm gate length. The on-current, delay time, and power-delay product of the optimized n- and p-type ML Bi2O2Se MOSFETs can reach or nearly reach the high performance requirements of the International Technology Roadmap for Semiconductors (ITRS) until the gate lengths are scaled down to 2 and 3 nm, respectively. The large on-currents of the n- and p-type ML Bi2O2Se MOSFETs are attributed to either the large effective carrier velocity (n-type) or the large density of states near the valence band maximum and special shape of the band structure (p-type). A new avenue is thus opened for the continuation of Moore's law down to 2–3 nm by utilizing ML Bi2O2Se as the channel.
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