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50 GHz static frequency divider in 130 nm CMOS

50 GHz static frequency divider in 130 nm CMOS

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© The Institution of Engineering and Technology
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A novel circuit topology and design procedure to increase the operating frequency of current model logic (CML) static frequency dividers is proposed. The topology and design procedure are used to design a 50 GHz CML static frequency divider in 130 nm CMOS. The designed divider has a 20 GHz division bandwidth and consumes 11.7 mW power from a 1.5 V supply.

Inspec keywords: integrated circuit design; CMOS integrated circuits; network topology; frequency dividers

Other keywords: power 11.7 mW; frequency 50 GHz; circuit topology; voltage 1.5 V; CMOS; size 130 nm; static frequency divider; bandwidth 20 GHz; circuit design

Subjects: Network topology; CMOS integrated circuits; Semiconductor integrated circuit design, layout, modelling and testing

References

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      • Plouchart, J.-O., Kim, J., Karam, V.: `Performance variation of a 66 GHz static CML divider in a 90 nm SOI CMOS', ISSCC Dig. Tech. Pprs, February 2006, San Francisco, CA, USA, p. 526–527.
    3. 3)
      • Lim, D., Kim, J.: `Performance variation of a 90 GHz static CML divider in a 65 nm SOI CMOS', ISSCC Dig. Tech. Pprs, February 2007, San Francisco, CA, USA, p. 542–543.
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      • Plouchart, J.-O.: `A power efficient 33 GHz 2∶1 static frequency divider in 0.12-µm SOI CMOS', IEEE Radio Frequency Integrated Circuit Conf., June 2003, Philadelphia, PA, USA, p. 329–332.
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      • Wohlmuth, H.-D., Kehrer, D.: `A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS', ESSCIRC 2002, September 2002, Florence, Italy, p. 823–826.
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