A general relation between zero-bias resistance - area product and perimeter-to-area ratio of the diodes in variable-area diode test structures

This paper is an attempt towards presenting a general analytical relation between the inverse of zero-bias resistance - area product and the perimeter-to-area ratio of the diodes in variable-area diode array test structures currently used in HgCdTe technology. Contributions from (i) surface leakage currents due to band bending at the HgCdTe surface (i.e. the HgCdTe - passivant interface), (ii) surface generation currents in the depletion region in the immediate proximity of the HgCdTe - passivant interface, (iii) surface leakage currents due to Zener tunnelling, (iv) leakage currents due to an imperfect HgCdTe epilayer - substrate interface and (v) bulk currents have all been taken into consideration in arriving at the relationship between the inverse of zero-bias resistance - area product and the perimeter-to-area (p/A) ratio of the diodes. The derived relation predicts in general a nonlinear behaviour of the data. It is shown by the detailed discussions that the general relation can be of great practical help in identifying the various possible mechanisms contributing to the surface leakage currents. Use of constant perimeter and variable-area (CPVA) test structures along with the usual variable perimeter and area (VPA) test structures to interpret the linear data, and additional experiments to distinguish the surface Zener tunnelling and surface generation - recombination mechanisms have been proposed. The previously reported data on variable-area test structures have been shown to fit very well with the presented model.