Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications

Memristor-based arrays composed of 1T1R cells were fabricated through the integration of CMOS transistors (N-type CMOS transistor in this case) and memristor devices. NMOS transistors were fabricated in 2.6 μm technology through a front-end-of-line process. Disk-shaped tantalum oxide TaO_x memristor devices with a diameter of ∼2 μm and as-deposited switching thickness of ∼14 nm were fabricated on top of the NMOS by a back-end-of line process. The TaO_x switching material was grown by reactive sputtering in a mixed atmosphere of Ar and O₂, and sandwiched between Ta/Pt electrodes. More details of the fabrication are provided in (Davila et al under preparation). A microscope image of the 4 × 4 array is shown in figure 1(a). Transistors are used in this design to allow for individual access of each memristor cell with minimized sneak path currents during cell programming and reading. This is critical for reaching accurate conductance values. During any computation function, all transistors are turned fully ON (with minimum drain to source resistance), making the crossbar act like a fully passive array. The gate electrodes (GE) are tied together for each column. In this manner, a single column or all columns may be activated simultaneously, depending on the operation.

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All electrical measurements were performed using a Keysight B1500 semiconductor parameter analyzer with the B1530 arbitrary waveform generator and fast measurement unit. LabView was used to control the instruments and implement the characterization and programming algorithms. For the DC characterization tests, the source measurement units from the B1500 were used for performing voltage sweeps and current measurements. For the pulsed characterization and algorithm implementation, all PP were applied through the B1530 arbitrary waveform generator while the currents were read using the B1500 source measurement unit (SMU).

Although it is possible to implement batch conductance programming arrays, in this work we focused our investigation on single cell operations. For programming the 1T1R cells in the array, only one cell is active at any given time. For example, as shown in figure 1(b), to connect the cell in the second row and second column, only pad 2 of BE and pad 1 of GE and TE should be active, while all other pads should be grounded. Figure 1(b) shows the array connection for a 1T1R cell under the SET and RESET operations. In the SET operation the voltage (V_set) is applied to the TE while the BE is connected to GND and, during RESET, the connections are reversed (V_reset is applied to BE). In both cases, GE is used to select the cell to be programmed by applying a high enough voltage (minimize the transistor series resistance), however, during the SET operation the transistor gate voltage (V_g-set) is an analog voltage that sets the current compliance. This is done in order to stop the SET switching dynamics and is a key component for controlled programming of the DPE. Figure 1(c) shows DC sweeps of SET and RESET operations for increasing V_g-set from 1.55 to 2.55 V. From the SET operation (the positive applied voltage sweep), increasing the gate voltage results in increasing current saturation, as expected for NMOS transistors. However, to calculate memristor conductance values in these SET curves is not straightforward, since the nonlinear series transistor resistance may contribute significant resistance. Thus, the conductance of the memristor is obtained by biasing the gates of the transistors to the highest voltage and applying a 0.1 V bias at BE (see figure 1(d)). It was found that V_g-set = 2.6 V was the highest gate voltage that resulted in a stable and switchable device for DC operation; higher voltages lead to very low resistance states that are not easily RESET. The current saturation in the SET curves of figure 1(c) is a result of the current limiting capabilities of the transistor in the saturation region, which results in a more controlled SET operation (low-to-high conductive state) (Lv et al 2015). A family of typical SET-RESET DC curves are shown in figure 1(c), where the device switches to various intermediate conductance levels.

One challenge that arises from memristive switching is the device variability, which has been reported by many research groups (Yang et al 2013, Kim et al 2015). The variability of the 1T1R cells used for the DPE in this work is shown in figure 1(d), where the low bias post-SET conductance of three cells is plotted as a function of gate voltage. All conductance values are measured at 0.1 V while applying the maximum gate voltage of 5 V. These conditions ensure both that there is no perturbation of the state due to high voltages and that the transistor is in its linear region (constant conductance of 2 mS). Amidst some cycle-to-cycle and device-to-device variability, figure 1(d) shows a clear and repeatable trend in the conductance-gate voltage relationship that can be leveraged into a model and programming algorithm for accurate tuning of the memristor's conductance. However, for any realistic application, programming of the conductance states needs to be accomplished at a fast rate rather than relying in slow quasi-static voltage sweeps. Thus, sub-microsecond PP are desired and were utilized here. Figure 2(a) shows conductance values as a function of V_g-set following SET-RESET switching using voltage PP of 100 ns. The V_set and V_reset voltage amplitude is 1.1 V and 1.4 V, respectively. For each V_g-set value, 10 SET and 10 RESET PP were applied to gauge cycle-to-cycle repeatability. Low bias quasi-static voltage sweeps are performed in between each programming pulse to obtain the post-SET and post-RESET conductance values. The results from figure 2(a) show similar behavior to those in figure 1(d) with the exception that higher V_g-set values are required to achieve a similar conductance state. This increase in voltage is expected since the switching time for tantalum oxide memristors decreases exponentially with voltage (Menzel et al 2011, Strachan et al 2013). The SET conductance (G_set) and V_g-set relationship of figure 2(a) can be modeled by a quadratic polynomial:

$$\begin{eqnarray}{V}_{{\rm{g}} \mbox{-} {\rm{s}}{\rm{e}}{\rm{t}}} & = & 2.037\,13\times {10}^{6}{G}_{{\rm{s}}{\rm{e}}{\rm{t}}}^{2}\\ & & +1.221\,42\times {10}^{3}{G}_{{\rm{s}}{\rm{e}}{\rm{t}}}+1.512\,91.\end{eqnarray} \tag{ 1 }$$

Which results in an adjusted R-squared of 0.990. This model is combined with an adaptive algorithm in order to accelerate the programming process.

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Figure 2(b) shows a detailed representation of the algorithm used for programming 1T1R cells. For clarity, only two conductance targets (G₁ and G₂) are shown, although the algorithm works with many more target values. Each TE and BE pulse represents a 100 ns programming pulse (SET and RESET directions, respectively). For a SET operation, the voltage at GE (V_g-set) is calculated from (1), in order to provide the required current compliance, while for a RESET operation, GE remains at V_g-reset = 5 V. A schematic of the 1T1R cell is shown in figure 2(b) with labeled connections and signals. The goal of the algorithm is to adaptively increase the applied voltage from 0.8 to 3.0 V in steps of 0.1 V (for either SET or RESET directions) until the measured conductance is within range of the target value (specified by a conductance tolerance (G_tol)). If the measured conductance overshoots the target (see change after vertical dashed lines in figure 2(b)), the direction of the applied voltage is reversed and initializes to its default value (0.8 V). The adaptive parameters for the algorithm may be further optimized based on the particular memristor's intrinsic dynamics. However, as shown, these already result in relatively fast programming of the states.

Experimental data for a sequence of programming targets using the proposed algorithm is shown in figure 2(c). In this experiment, the algorithm programs the 1T1R conductance to seven randomly selected values. The conductance is successfully programmed if it is within 8 μS of the target (denoted by the solid circles in the G plot in figure 2(c)). During the SET operation (applied pulses to TE), the algorithm adaptively changes the value of GE depending on the target conductance. It has been shown that the programming speed (number of pulses needed to successfully program a conductance value) in 1R cells is greatly affected by the voltage step parameter (Alibart et al 2012). However, the results from figure 2(c) show that by utilizing the current compliance capabilities of the 1T1R cells as a variable in the algorithm a 10× increase in the step voltage can still be used while minimizing the risk of overshoot. This results in much accelerated memristor programming.

The programming algorithm and the model from equation (1) are then used to successfully program 64 conductance targets (G_t) in a 1T1R cell and 16 conductance targets in four different cells in a 4 × 4 array (see figures 3(a) and (b)). The levels are linearly spaced between 100 and 700 μS with G_tol set to 1 and 8 μS for the 64 level and 16 level cells, respectively. Each cell is cycled 10 times between all levels and between each cycle the order of the targets is randomized. The randomization is performed to prevent correlations between algorithm performance and target order. These results show that a single TaO_x memristor cell can be accurately and repeatedly programmed to represent 6 bit values with very high accuracy. For the 64 level case, an average accuracy of 0.44% is obtained with a worst case accuracy of 1.62% at the lowest conductance level. Medians of the number of PP and OS as a function of G_t for all cells are shown in figure 3(c). Programming larger number of conductance levels requires smaller G_tol in order to obtain distinguishable conductance levels, which in turn results in larger number of PP and OS required to reach G_t. A significant accomplishment is that the algorithm performs similarly in all 4–16 level cells, even with the same V_g-set–G_set model used without any customization for the particular cell. In general, PP slightly increases for G_t smaller than 300 μS for all cells, which may be due to the higher cycle-to-cycle variability of the SET operation at smaller V_g-set (see figure 2(a)). This results in more programming attempts needed to reach smaller conductance values. The OS is another important quantity when using adaptive feedback algorithms, since it is a measure of system instability (Nise 2015). If this measure is not controlled, the system may result in ringing or ripple in the vicinity of G_t, which directly affects the number of PP required. Some variation in OS is observed between different cells with higher values for decreasing G_t (see figure 3(c)). Medians of the number of PP and OS at various G_tol are plotted in figure 3(d). Both parameters can be modeled by the following two exponentially decaying functions:

$$\begin{eqnarray}&&{\rm{P}}{\rm{P}}=1.71775\,+\,12.83088{{\rm{e}}}^{(-110803.32{G}_{{\rm{t}}{\rm{o}}{\rm{l}}})},\,\end{eqnarray} \tag{ 2 }$$

$$\begin{eqnarray}&&{\rm{O}}{\rm{S}}=0.32113\,+\,5.24627{{\rm{e}}}^{(-166278.68{G}_{{\rm{t}}{\rm{o}}{\rm{l}}})}.\,\end{eqnarray} \tag{ 3 }$$

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Note that equations (2) and (3) may also be dependent on the pulse width, initial voltage, and step voltage used in the algorithm (Strachan et al 2013). For example, using an initial voltage of 0.5 V instead of 0.8 V increases the medians of the number of PP for all targets from 7.5 to 12, respectively. However, using an initial voltage of 1.2 V results in constant overshoot with some of the targets not being reached. Thus, care must be taken when choosing the programming parameters in order to find optimal conditions applicable to all cells in the DPE, and this will vary based on the memristive system utilized. In addition, other important performance metrics for the DPE computation, such as state retention and cell endurance, may be strongly affected by the programming parameters.

The programming speed on 1T1R cells is further improved by first performing an initialization pulse followed by the original algorithm. The initialization pulse consists of either a 'hard' RESET (HR) or a 'hard' SET (HS) pulse of 1.75 V and 1.4 V, respectively, depending on the direction of the conductance target from the current conductance. The word 'hard' in the adopted naming convention is used to emphasize that a high voltage is used in the first programming attempt. During the HS pulse, the amplitude of V_g-set is obtained from equation (1). A representation of the HR and HS algorithm is shown in figure 4(a). Note that the initialization pulse is only performed when changing conductance targets and is always followed by the original algorithm. Results for medians of PP and OS using the HR and HS algorithm (from figure 4(a)), the original algorithm (from figure 2(b)), and a voltage ramping algorithm constant V_g-set = 5 V (no SET switching control) are shown in figure 4(b). All other parameters of the algorithms are the same in all three cases. The measurements were performed on the same cell using 16 target conductance values that were cycled 10 times and randomized between each cycle. The improved performance of both proposed algorithms over one without adaptive V_g-set is approximately 10×. The average PP for all 16 levels is approximately 32 and 3 for the open gate and HR and HS algorithms, respectively. The speed-up is due to avoiding the frequent overshooting of the conductance value from the highly nonlinear SET switching operation observed in most memristors. The OS could be minimized by decreasing the voltage step size in the algorithm, however, doing so results in more programming attempts. There is a slight overall improvement of the HR and HS algorithm over the original version in terms of PP. This improvement is most likely due to two effects: (1) if HR is performed, the cell will be programmed to a low conductance state (and most likely the conductance will overshoot the target) followed by a controlled SET using the original algorithm, or (2) if HS is performed, the resulting conductance change is larger due to the higher applied voltage, but the switching is still controlled by V_g-set. In both cases, the conductance converges faster to the target values as seen in figure 4(b). The HR and HS algorithm results in an increased number of OS compared to the original version, which is a natural consequence of the HS/HR performed. This may ultimately have an impact on the relative endurance of the devices, which was not compared in this work.

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So far, the performed experiments are targeted for DPE applications that require a high level of accuracy in the programmed conductance, such as in analog acceleration of mathematical operations. However, other learning applications, such as neural networks, in many cases require tuning of the conductance in the right direction during the learning process rather than attaining highly accurate values (Prezioso et al 2015). The results from figure 2(a) suggests that with only 2 pulses the conductance values are changed or converge towards a specific value. To further explore this conductance tuning, a series of experiments are performed where the number of PP is limited to 2, 3, and 6 pulses using the HR and HS algorithm. This algorithm is chosen because it resulted in the smallest overall number of PP from the previous experiments (see figure 4(b)). Figure 4(c) shows the accuracy (programming error) of all 16 targets after a limited number of programming attempts are performed. The overall error decreases with increased number of PP, however, even with PP = 2 the resulting conductance is tuned towards the desired value. A two-pulse programming cycle for the 16 conductance levels is shown in figure 4(d). For each target, the initial, post-first pulse, and post-second pulse conductance values are shown, which highlights the conductance trajectory. This suggests that for neural networks based on the DPE, programming speeds throughout the neural network training epochs can be further increased, paving the way for fast training. Additionally, the future arrays will support batch precision programming of entire rows at one time, with independent control of each cell's gate voltage. This can be done by modifying our architecture: design the array with horizontal TE traces (similar to the BE), while keeping the vertical GE traces. In this manner, all the cells in a given row can be programmed simultaneously with independent gate control.

An important figure of merit for memory cells is their cycling endurance, especially for accelerator applications that may require frequent re-tuning of cell conductances. The endurance for three 1T1R cells at different V_g-set values is shown in figure 5(a). Each boxplot at each V_g-set is a distribution of 1 million cycles performed in open-loop, i.e. using a single 200 ns pulse for SET and RESET. The values for V_set and V_reset are 1.2 V and 1.5 V, respectively, with V_g-reset equal to 5 V. These results show that our tantalum oxide 1T1R cells are able to cycle more than 1 million times without failure. The conductances as a function of endurance cycle for one of the cells is shown in figure 5(b). These results agree with those of figure 2(a), but provide much more statistical information given the high number of cycles.

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