Diamond power devices: state of the art, modelling, figures of merit and future perspective

Diamond crystals are usually classified on the basis of the type of impurity concentration (nitrogen and boron) and their arrangement in the crystalline structure. An accurate classification of diamond crystals can be found in table 2 and it applies to both natural and synthetic diamonds (HPHT or CVD).

The HPHT technique for the realization of synthetic diamond substrates allows us to achieve high purity with a low defect density, but the total size (between 2  ×  2 mm² up to 10  ×  10mm² for IIa) is restricted due to intrinsic limitations of this method. HPHT substrates used for electronic devices are usually type Ib due to their relatively low cost and low dislocation density of about 10⁵cm⁻², but type IIa substrates can achieve even lower dislocation density (<10³ cm⁻²) with drawbacks in terms of the complex fabrication process and cost. CVD growth has fewer limitations on the size of the substrate (up to 0.5 inch) despite the fact that CVD does not allow us to achieve the same crystalline quality of the HPHT technique. Over 2 inch CVD substrates can be found in a mosaic configuration, but the bonding boundaries between the wafers can limit the electrical performance of the device and increase strain and defects in the structure [22]. An alternative technique to homoepitaxial growth is the heteroepitaxial growth of diamond on iridium (Ir) and other similar substrates [23, 24]. This process allows us to reach over 3 inch substrates, but with a high dislocation density (between 10⁷–10⁹ cm⁻²).

Due to the peculiar lattice structure and material strength, only shallow doping profiles (<10 nm) can be obtained by means of a high-energy ion implantation process in diamond [25, 26]. Recently, thermal doping diffusion has been proven and a diamond p–n diode based on this doping technique has been fabricated and characterized [27, 28]. However, these techniques require further investigation prior to becoming a reliable method of fabrication. Therefore, the incorporation of substitutional dopant species during the growth of diamond layers is mainly realized simultaneously with the CVD growth. Low boron concentrations (10¹⁵ cm⁻³) are relatively easy to implement, but the fabrication of thick doped p-type layers remains challenging due to the loss of the crystallinity. While boron forms an acceptor level at 0.38 eV from the maximum energy level of the valence band (E_va), nitrogen and phosphorus n-type dopants result in a much deeper energy level from the conduction band minimum (1.7 and 0.57 eV from E_co, respectively). At the electro-thermal equilibrium, it is possible to solve the charge-balance equation (with the Fermi statistic) to calculate the total number of holes (or electrons) for different temperature and compensation doping [29, 30]. This is shown in figures 2(a) and (b). As can be observed, compensation plays a key role in the determination of the hole concentration. Besides, as discussed in [29], the mobility and overall resistivity of the diamond layers are also affected by the compensation level. Nevertheless, the substantial progress in the CVD growth of homoepitaxial grown has allowed for ultra-low compensated boron diamond layers (<1%), even for low dopant density. Such compensation values, which have been achieved by many research groups [31–33], are however still difficult to obtain with phosphorous-doped layers. Therefore, as all the subsequent results and calculations shown in this manuscript will consider boron-doped layers, compensation will be neglected. However, it is worth mentioning that all the results can be easily extended in the case of non-negligible dopant compensation.

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The growth of phosphorous-doped diamond layer ensures lower resistivity for n-type layers, but it requires high and controlled temperature during the whole growth process [36]. Although it is possible to obtain a relatively wide doping window, heavy n-type (>5  ×  10¹⁹ cm⁻³) doping still remains challenging [37] (table 3). In addition, the crystal orientation also plays a key role in determining the quality of the doped and intrinsic layers. The 〈1 0 0〉 orientation is the most common for growing diamond layers. However, it is still complicated to grow n-type layers and there are still limitations in the efficiency of p-type doping. Conversely, in the 〈1 1 1〉 direction, n-type phosphorous dopants can be incorporated more easily and it is possible to achieve one of the highest boron concentrations [38]. Nevertheless, one of the significant drawbacks of the 〈1 1 1〉 orientation is the formation of macroscopic defects, which leads to a poorer quality of the material [39]. On 〈1 1 0〉 faces, boron concentration can be improved if compared with 〈1 0 0〉 but the reduced surface area hampers the benefits due to the enhanced doping control. Other orientations such as〈1 1 3〉, which have not been deeply investigated yet, may result in enhanced control and speed for the doping process of diamond layers. Macroscopic and microscopic defects are also playing a key role in determining the electrical properties [40, 41]. Non-epitaxial crystallites, which are a typical feature of homoepitaxial grown diamond, have already been demonstrated to affect the performance of metal-semiconductor FETs (MESFETs), metal oxide semiconductor (MOS) and Schottky diamond diodes [42–45]. For a complete review of diamond defects and their characterization techniques, the reader can refer to [46].

2.3.1. Oxygen termination.

2.3.2. Hydrogen termination.

Among the possibilities that allow us to obtain an RT fully activated diamond channel, heterojunctions between diamond and group III nitrides (AlN, GaN and BN) are one of the most promising and attractive configurations. As the growth of GaN layers on diamond surfaces is complicated, AlN and BN have been identified as the best materials for diamond heterojunctions. Kuech et al [59] reported an H-terminated diamond surface with an AlN passivation layer and the first demonstration of an AlN/diamond heterojunction n–p diode was successfully carried out by Miskys et al [60] by using a molecular beam epitaxy technique. As the H-terminated surface results in a poor attachment to the AlN layer, an O-terminated diamond surface was adopted for the first AlN/diamond heterojunction FET realized by Imura et al [61, 62] with a metal-organic vapor-phase epitaxy technique.

Discrepancies between time-resolved cyclotron resonance (TRCR), time-of-flight (TOF) and Hall measurements have generated confusion about the real value of diamond carrier mobility with overestimations for hole and electron mobility at RT (7300 cm² V⁻¹ s⁻¹ for electron and 5300 cm² V⁻¹ s⁻¹ for hole [63]). More specifically, Hall electron mobility values calculated at RT oscillate around 1000 cm² V⁻¹ s⁻¹, whilst TOF performed by Isberg et al [64] shows higher electron mobility, an overestimation which may be caused by the approximation of Hall scattering factor, as suggested by Pernot [65]. Regarding the electron mobility in n-type layers, intra-valley phonon scattering is the dominant scattering mechanism in the HT range (regardless of the doping level of the layer), while the interaction with the intra-valley acoustic phonon is the main scattering mechanism in the middle temperature range [65, 66]. In the low-temperature range, ionized impurity and neutral impurity scattering are the main scattering mechanisms. Conversely, hole mobility is subjected to the same scattering mechanisms in the low-temperature range, while intra-band and inter-band acoustic phonon scattering dominate the medium range, and the interaction with the optical phonon is the main mechanism responsible for the mobility at HT.

Regarding the hole mobility, some discrepancies between TOF, TRCR and Hall measurements still persist with values ranging between 3800 and 2100 cm² V⁻¹ s⁻¹ at RT with a tendency of measurements to confirm the 2100 cm² V⁻¹ s⁻¹ value [65, 68] (figure 3(a)). However, recent measurements tend to agree on the RT values for electron/hole mobilities [31, 32].

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Such mobility values can be reached in pure or low-doped diamond, where the limiting mobility mechanism is purely intrinsic due to phonon scattering mechanisms. Detailed analysis of the mobility dependence versus doping level concerning phosphorus-doped n-type [66] and boron-doped p-type [29, 69, 70] materials have been reported. In uncompensated and highly doped material, the neutral impurity scattering is the dominant scattering mechanism because of the large ionization energy of the donor and acceptor dopants. In figure 4, the hole mobility has been plotted as a function of the temperature doping with the fitted models from [66, 70].

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Few studies have analyzed the mobility in hydrogen-terminated diamond surfaces. In general, extraction of the conductivity (carrier sheet density and mobility) is obtained during the electrical characterization of the 2DHG FETs. Besides, values of surface channel p-type channel FETs rarely exceed 200–300 cm² V⁻¹ s⁻¹ due to surface roughness, ionized impurity scattering and the high-surface electric field generated by the presence of the negatively charged acceptors, which cause the confinement of the 2DHG (figure 3(b)). Recently, Li et al [71] calculated the 2DHG mobility as a function of the temperature and hole gas density and then compared their theoretical results with a variety of experiments.

Mobility extraction has been also performed on delta-doped FETs showing that the predicted enhanced mobility in such layers cannot be achieved and values rarely exceed 20 cm² V⁻¹ s⁻¹ [72]. On C–OH diamond surfaces, the mobility of the inversion layer on lateral metal-oxide semiconductor field-effect transistors (MOSFETs) has been estimated to be 8 cm² V⁻¹ s⁻¹ due to the non-optimal quality of the diamond/Al₂0₃ oxide interface [73].

Power semiconductor devices are characterized by conduction, switching and OFF state losses. A perfect figure of merit (FOM) would take each contribution into account, with specific interactions at the system level (i.e. thermal, driving, electromagnetic compatibility (EMC), reliability, sourcing and cost). Unfortunately, it is almost impossible to compare different devices based on different technologies and/or materials based on a simple FOM. As an example, switching losses are not only dependent on the power device itself, but the driving circuit, topology employed (e.g. based on soft or hard switching) and parasitics associated with packaging. One of the most used FOMs in power semiconductor devices is Baliga's figure of merit (BFOM) defined in [74] and equation (1). This BFOM has been derived from the specific ON state resistance (equation (2)), which can be expressed by equation (3) in the case of several assumptions. Consequently, equation (3) introduces the BFOM in the typical trade-off between the specific ON state resistance (R_{on_spec}) and the BV. However, the assumptions required to directly relate the BFOM to the R_{on_spec} cannot apply in the context of diamond power devices; in diamond bulk devices, the incomplete ionization of dopants, and in 2DHG devices, the sheet carrier concentration and specific 2DHG mobility must be considered. Consequently, equation (3) is no longer valid and the specific R_{on_spec} is no longer derived by the BFOM. In equations (1)–(3), µ_n is the mobility of electrons (µ_p of holes), ε is the dielectric permittivity of diamond, E_c is the critical electric field (table 1), ρ_Drift is the resistivity, S is the active area, L_Drift is the length of the drift region and q is the electron charge.

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {\rm BFOM}={{\mu }_{{\rm n,p}}}\cdot \varepsilon \cdot E_{{\rm c}}^{3},\nonumber \end{align} \tag{ 1 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle ({\rm General}\,{\rm case}):{{R}_{{\rm ON }\_{\rm spec}}}={{R}_{{\rm ON}}}S={{\rho }_{{\rm Drift}}}\cdot {{L}_{{\rm Drift}}}=\frac{{{L}_{{\rm Drift}}}}{q\cdot ({{\mu }_{{\rm n,p}}}\cdot n,p)},\nonumber \end{align} \tag{ 2 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle ({\rm With}\,{\rm assumptions}):{{R}_{{\rm ON }\_{\rm spec}}}=\frac{4\cdot B{{V}^{2}}}{{{\mu }_{{\rm n,p}}}\cdot \varepsilon \cdot E_{{\rm c}}^{3}}=\frac{4\cdot B{{V}^{2}}}{{\rm BFOM}}.\nonumber \end{align} \tag{ 3 }$$

Consequently, the specific ON state resistance (R_{on_spec}) is used as a FOM to compare different devices or materials, for a given range of BVs. The ON state resistance is typically measured by pulsed I–V or calculated based on analytical formula or numerical analyses. The device area is extracted from the active area (S) or device area, either including or not including the termination region. The BV is measured or calculated based on specific hypotheses. There are mainly four issues with the direct comparison of the R_{on_spec} value among different devices or materials at the same BV and the use of R_on__spec as a FOM: the lack of direct switching loss estimation, the different assumptions related to R_on, S and BV between devices or materials, the lack of link with the thermal conductivity and the scalability of R_on with the surface. The junction temperature at which the comparison is carried out must also be discussed.

In order to relate the FOM to the switching losses, other FOMs such as R_on · Q_g (or Q_gd, Q_oss) have been introduced [1, 75, 76]. These FOMs are clearly more complex than the R_on__spec FOM alone, albeit harder to predict for diamond power devices. Indeed, actual diamond power devices still have small active areas, which makes difficult a precise measurement of the capacitances related to the active area. These FOMs are best suited to unipolar devices, but cannot be used in the context of bipolar devices due to recovery charges and their impact on switching losses. Specific studies are required on diamond power device optimization and measurements, to further demonstrate low gate charge (Q_g), gate-drain charge (Q_gd) and output charge (Q_oss) (output charge), whereas most of the recent achievements concentrated on reductions in R_{on_spec}. Accordingly, the control of the Miller ratio between the Q_gd and Q_gs is also an important criterion to consider. Immunity to dV/dt and dI/dt and the maximum turn ON and turn OFF switching speeds are equally relevant. Besides these parameters, the gate leakage must also be considered.

While estimating the conduction loss is straightforward with appropriate conduction models, the prediction of switching losses highly depends on multiple parameters such as the parasitic capacitances, gate driver parameters (e.g. transconductance, min and max gate voltage) and circuit elements (e.g. parasitic inductances and capacitances). A fair comparison for switching losses must include similar EMC/electromagnetic interference (EMI) constraints, as large gate currents in MOSFET will lead to reduced switching losses, but very high dV/dt and dI/dt values. Such high transient values can have negative impacts on motors, cables and common mode filters [77], and can cause false switching through the Miller capacitance [78]. Moreover, to date there have been no studies on the switching losses in diamond FETs, mainly due to the limited availability and small size of diamond FETs. A fair comparison of the switching losses among power devices based on different materials will depend on the specific application. There are however a few case studies of diamond diodes in power commutation cells [79–81], mainly on diamond Schottky barrier diodes (SBDs) showing small recovery-like currents due to the diode intrinsic transition capacitance. The main problem in performing these experiments is to associate small-size diamond diodes with power FETs having similar voltage capability and parasitic capacitances. The small signal and large signal characterization of diamond FETs are then highly desired to be able to benchmark accurately the performances of diamond power devices [82, 83].

The expected benefits for power electronics with unipolar diamond or UWBG devices are to be able to match the conduction loss of silicon bipolar devices. Given the unipolar conduction and the absence of excess charge in the ON state, the switching losses could be dramatically reduced. As presented in section 5.3, the benefits of bipolar diamond devices with an efficient resistivity modulation will be limited to ultra-high voltage and low switching frequency, due to the large built-in potential in diamond and short carrier lifetimes. Consequently, unipolar diamond devices are expected to have the highest impact at system level in the short- to mid-term. Despite the issues related to switching loss predictions with diamond power devices discussed hereinbefore, one can assume several hypotheses to predict the switching performances of diamond unipolar power devices; the turn OFF losses with diamond FETs will be neglected as the channel current is turned OFF very quickly thanks to the smaller input capacitance (smaller active area) and the high transconductance; the turn ON losses are not limited by EMI issues; the drift region is considered in NPT configuration; the device is of vertical type. As a result, the lowest possible switching losses in a power FET are governed by the stored electric charge in the output capacitance (C_oss) during the switching transition, where the C_oss as a function of V_DS can be expressed by equations (4) and (5). In equation (4), ${{C}_{{\rm OSS}\left({\rm V} \right)}}$ is the output capacitance as a function of the bias, which is typically the transition capacitance ${{C}_{{\rm T}\left({\rm V} \right)}}$ exhibiting a square root dependence with bias when the drift region is in NPT condition. At the BV, the transition capacitance ${{C}_{{\rm T}\left({\rm BV} \right)}}$ is calculated by equation (5), with $\newcommand{\e}{{\rm e}} {{\epsilon }_{0}}\times {{\epsilon }_{{\rm r}}}$ the permittivity of diamond, S the active area and ${{d}_{{\rm Drift}}}$ the thickness of the drift region. Whereas two FETs or one FET and one diode will be associated in a power commutation cell. The active area of each power device can be different as a function of the duty cycle. As a consequence, only the C_oss of one power device can be considered for the estimation of the minimum power losses ${{P}_{{\rm sw}{\rm .on}}}$, as proposed for example in [84] and equation (6), where $V$ is the switched voltage and f  the switching frequency.

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{C}_{{\rm OSS}\left(V \right)}}={{C}_{{\rm T(V)}}}={{C}_{{\rm T}\left({\rm BV} \right)}}\sqrt{\frac{{\rm BV}}{V}},\nonumber \end{align} \tag{ 4 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{C}_{{\rm T(BV)}}}={{\epsilon }_{0}}\times {{\epsilon }_{{\rm r}}}\times \frac{S}{{{d}_{{\rm Drift}}}}=C_{{\rm T(BV)}}^{*}\times S,\nonumber \end{align} \tag{ 5 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{{\rm sw}{\rm .on}}}\left(V \right)=\frac{2}{3}\times {{C}_{{\rm T}\left({\rm BV} \right)}}\times \sqrt{BV}\times {{V}^{\frac{3}{2}}}\times f.\nonumber \end{align} \tag{ 6 }$$

In an actual application, the best power device is the one minimizing total losses while respecting key constraints (e.g. maximum junction temperature and power density). Therefore, the optimal device area minimizing the sum of switching losses (given by (6)) and conduction losses (related to (2) or (3)) can be determined for a fixed set of specifications (switching frequency, BV, rated current, NPT profile) thanks to the models and discussions presented earlier in this section and in other articles such as [84]. Figure 5 shows an example of a 1.7 kV diamond vertical unipolar power FET, switching 1200 V–50 A at 20 kHz or 100 kHz, with a maximum junction temperature of 425 K/450 K and a duty cycle of 0.5. At the optimal area of 0.25 cm² (20 kHz), the total losses represent 12 W (0.04% of switched power), the current density in ON state is 200 A cm⁻² and the total power loss density is 54 W cm⁻² (similar results are observed between T  =  425 K and 450 K). If the switching frequency is increased up to 100 kHz, the optimal area becomes 0.1 cm², the total losses 27W, the current density in ON state 500 A cm⁻² and the total power loss density 270 W cm⁻² (figure 5(a)). If this power density is too high for the thermal spreader, the active area must be increased, in the price of increased total power losses, or the switching frequency must be reduced. This simple approach can be applied to compare different devices or materials for the same specifications. As an example, a commercially available 1700 V SiC MOSFET has been chosen for [85] and while applying the same modelling, figure 5(b) presents the performances for both materials under the same specifications (20 kHz switching frequency). The diamond device will be almost ten times smaller, with more than three times lower total losses than SiC. This is even done at a higher temperature of 450 K for diamond compared to 425 K for SiC, which is also a huge benefit at the system level (see section 5).

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Considering that power loss density is still around or below 50 W cm⁻², the switching frequency can be increased up to 100 kHz—see table 4 for the complete analysis. At both optimal design points, the total losses with diamond switching at 100 kHz with a junction temperature of 450 K are still smaller than the total losses of SiC switching at 20 kHz. However, the power density has been increased from 20 W cm⁻² in 20 kHz SiC to 270 W cm⁻² with the 100 kHz diamond. Increasing the diamond area above the optimal area will increase the total losses, while slightly decreasing the power density. In this example, it is possible to reduce the power density in diamond from 270 to 153 W cm⁻², while increasing the active area from the optimal value of 0.1 cm²–0.26 cm². At this 'non-optimal' design (in terms of total loss), the total loss in diamond at 100 kHz is the same as the SiC operating at 20 kHz for the same switched current and voltage. To conclude this analysis, a global comparison can be proposed and is represented in figure 6: the performance of diamond power devices is highlighted here, while offering at the same time, smaller active areas, smaller total losses, larger current densities and higher junction temperatures. Table 5 shows the comparison of diamond and SiC under the same switching conditions at RT, where the benefits of diamond are reduced due to the high activation energy (no compensation is assumed). In spite of the benefits of diamond in terms of total losses and active area, the power loss density has been increased by 250%.

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Please note that in these comparisons, the following parameters for the SiC MOSFET have been taken from its datasheet: initial active area of 0.3 cm² (overestimate of active area), with an ON state resistance of 100 and 50 mΩ, respectively at 425 K and RT, 180 pF parasitic output capacitance at 1 kV. The performance of the SiC MOSFET has been linearly scaled and compared with diamond at the optimal area under the same operating conditions.

Due to the low incorporation of phosphorous and the high activation energies for n-type dopants, diamond Schottky diodes have been mainly fabricated on boron-doped layers. Fewer benefits would be obtained with bipolar devices due the high built-in voltage of the p–n junctions (table 1), which would result in a significant ON state voltage drop. The bipolar mode could only be of use in ultra-high-voltage applications (above 10 kV) and low-medium-frequency applications, as it will be discussed in section 5.3. Manufactured diodes have been reported, featuring both unipolar action such as Schottky, metal-intrinsic-P (MIP), Schottky p–n diode (SPND) and bipolar action such as p–n junctions and PIN diodes (figure 7).

Regarding p-type diamond Schottky diodes, high blocking voltages (up to 10 kV [86]) and critical electric field (7.7 MV cm⁻¹ [21]) have been reported in the literature, but a significant non-uniformity in the material quality has resulted in discrepancies for the reported experiments. Record currents of several amperes have been measured for a few packaged diodes [9] and HT operations (over 525 K) have been experimentally demonstrated with no observed degradation of the Schottky properties [21, 42, 50, 53, 87–92]. The difficulty in obtaining large-size self-standing low-resistive single crystal has resulted in the development of pseudo-vertical diamond structures (figure 7), where the p  +  + layers, on which the ohmic contact is deposited, is grown on top of the HPHT substrate. Various metals (W, Zr, Cu, etc) and surface treatments have been explored in order to optimize the rectification behavior [93–95], to improve the uniformity of the Schottky metal [42] and to reduce the leakage currents, which result in premature breakdown [53, 96, 97]. The best trade-off obtained so far has been achieved with Zr (table 6) [21] for pseudo-vertical diamond diodes, while a 5 A, >1 kV vertical diode has been demonstrated in [87] with Pt Schottky metal.

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Diamond vertical PIN diodes have been successfully reported in [98–101]. Together with the lack of carrier lifetime control, reproducibility and uniformity, the high built-in voltage of the p–n junction (even when operated at HT) represents a limiting factor in the development of this device structure [102]. To overcome some of the previously mentioned issues, Schottky p–n type diodes have been suggested [103–106]. The Schottky metal on top of the n-type layer is able to deplete the n-type (nitrogen or phosphorous) doped layer in both the ON state and OFF state, allowing for holes to be injected from the p+  layer in the ON state and at the same time support the reverse voltage.

The ideal MOS structure requires an electrostatic potential barrier, which hinders the carrier transport from the semiconductor to the gate metal. Depending on the carrier transport mechanisms and specific characteristics of the device, it could also be possible to provide a single potential barrier with respect to the conduction or the valence band. This is the case for H-terminated diamond FETs where a single barrier for 2DHG is required [116]. Double- and triple-oxide stacks have also been investigated on H-terminated diamond surfaces, and their electrical properties (i.e. hysteresis, band offset, leakage) accurately reviewed in [117]. A schematic band alignment computed with the procedure and the parameters defined in [118, 119] has been plotted in figure 8 for both H-terminated(a) and O-terminated(b) diamond. As can be noted, only a few oxides (such as SiO₂, Al₂O₃) would allow for a dual barrier with the conduction and valence band of O-terminated diamond. Moreover, despite the fact that numerous diamond-oxide interfaces have been studied in the last fest years [117, 120], the lack of native oxides for diamond has often resulted in highly defective interfaces, which have negatively impacted the carrier mobility at the interface.

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4.2.1.1. Oxygen-terminated diamond MOS regimes and reliability.

4.2.1.2. Deep depletion and inversion mode MOSFETs.

Among the properties correlated with the wide value of the diamond band gap (5.47 eV at RT), the small value of the intrinsic carrier concentration has a positive effect on reducing the thermally generated minority carriers for the creation of inversion regime formed in the MOSFET devices [124]. More specifically, if minority carriers are not provided by source and drain regions or by UV light exposure, a deep depletion regime can be obtained for a long and stable duration. The concept of temperature-time stable deep depletion effect observed and demonstrated for diamond devices is different to the dynamic effect described in other semiconductors such as silicon [125–128]. In this case, the inversion layer is much more sensitive to time and temperature effects, making deep depletion only a transient effect able to improve the dynamic BV. Experimental deep depletion diamond MOSFETs rely on the Al₂O₃/(Ti/Pt/Au) stack. High breakdown fields of 4 MV cm⁻¹ have been measured for a lateral normally-ON device, as schematically depicted in figure 9. However, the maximum current density observed in [129] is several orders of magnitude lower than the one reached for H-terminated FETs.

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Recent reports have demonstrated the possibility of realizing deep depletion diamond Fin-FET with CVD boron doping on a 〈1 0 0〉 3  ×  3 mm² HPHT undoped substrate. E-beam lithography and O₂ dry etching have been used to fabricate the Fin-FET structure depicted in figure 9. The low value of the boron concentration in the channel (5  ×  10¹⁶ cm⁻³) together with the 45 nm of SiO₂ oxide and the small metal work function of Al (≈4.08 eV) result in a depletion width of about 55 nm. As the depletion region width is more than half the fin channel width, the device exhibits normally-OFF behavior.

High quality p-doped n-type diamond body/Al₂O₃ interface obtained by wet annealing has resulted in the first diamond inversion-type lateral MOSFET on a 〈1 1 1〉 HPHT substrate, as reported by Matsumoto et al [73]. A maximum drain current density of 1.6 mA mm⁻¹ and channel field-effect mobility of 8 cm² V⁻¹ s⁻¹ have been extracted from the experimental data at VGS  =  −12 V and VD  =  −5 V (table 7). This proof of concept for an inversion mode MOSFET resulted in a normally-OFF behavior, with a negative threshold voltage (Vth) of about  −6.3 V. This high Vth value for the inversion regime is a clear signature of high level of interface traps (with a density estimated to be above 6  ×  10¹² cm⁻² eV⁻¹).

Table 7. State-of-the-art parameters and key features for diamond depletion and inversion mode MOSFETs depicted in figure 9.

Device	Vertical FinFET	Lateral deep depletion MOSFET	Lateral inversion mode MOSFET
Breakdown voltage	>16 V at T  =  300 K [130]	>200 V at T  =  300 K [129, 131]	<50 V at T  =  300 K [73]
Current densitya	<1 mA mm−1 at T  =  300 K	≈0.1 mA mm−1 at T  =  300 K with VDS  =  −15 V and VGS  =  −16 V [131]	<1 mA mm−1 at T  =  300 K
	<10 mA mm−1 at T  =  450 K with VDS  =  −15 V and VGS  =  −16 V [130]	<1  ×  10−3 mA mm−1 at T  =  300 K	With VGS  =  −5 V VDS  =  −1 V [73]
	<0.05 mA mm−1 T  =  300 K	≈5  ×  10−3 mA mm−1 at T  =  450 K with VGS  =  −10 V VDS  =  −1 V
	<2 mA mm−1 at T  =  450 K with VGS  =  −10 V VDS  =  −1 V	With selective growth of P+  :  ≈3 mA mm−1 at T  =  523 K with VGS  =  0 V VDS  =  −1 V
Notes	Fin channel allows for normally-OFF operation.	Normally-ON.	Normally-OFF
		HT operation increases the current and reduces the threshold voltage	Low interface mobility
	BVmeasurements are not reported. However, gate and drain overlap limits the max BV	Scaling of the Ron_spec and BV is an issue	High density of traps
	Max observed drain current is limited to 838 nA for VGS  =  VDS  =  −16 V at T  =  300 K and 29 µA at 450 K [130]	Field plates are needed to improve the BV	Low BV
		Current density is limited by the incomplete ionization at RT	First proof of concept

^aValues reported for the Fin-FET are assuming the true width of the current transport path.

4.2.2. Junction FETs (JFETs), MESFETs and bipolar transistors.

FETs based on MESFET or p–n JFET are highly reliable for power electronics applications due to the absence of the gate oxide layer, which tends to generate high-density interface states and trapping/de-trapping mechanisms (figure 10). Umezawa et al [132] have fabricated several diamond MESFETs, exploring different Schottky gate metals (Mo, Pt, Al) and observed a maximum current density of 1.2 mA mm⁻¹ at HT (T  =  600 K) with VGS  =  0 V and VDS  =  −20 V due to the enhanced boron activation in the conduction region. High BVs above 2 kV with a gate to drain distance of 50 µm [133]) have been shown for diamond MESFETs, which usually exhibit normally-ON characteristics with a high threshold voltage (Vth). Good scalability of the BV with the gate drain distance has been proven for diamond MESFETs [132]. Diamond MESFETs have also been realized in reverse blocking configurations with a Schottky metal for the gate and the drain contacts [134].

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On the other hand, improvements in the lateral growth of n-type diamond layer in the 〈1 1 1〉 direction have enabled the fabrication of high-quality diamond p–n+  junction with high rectification ratio and BVs close to 1 kV [37, 39, 48, 135, 136]. These p–n  +  junctions have been used as the building block of diamond JFET fabricated by Hosino et al [39]. Different channel width and doping levels have resulted in both normally-ON and normally-OFF devices demonstrated in unipolar and bipolar conduction mode. The BV measured at different junction temperatures shows a positive coefficient, according to the increase of the phonon scattering and consequent reduction of the avalanche multiplication coefficient [135]. Normally-OFF JFETs (with a Vth around  −1.2 V) have been manufactured by implementing a parallel reduction of the doping concentration and the channel width (≈0.2 µm) in order to pinch-off the channel at zero bias. Devices show a good rectification ratio, but a much smaller current density due to the higher resistivity of the channel region [137]. Despite the current density increases at HT, a positive shift of the threshold voltage with the temperature, which has also been confirmed by TCAD simulations and experimental results [35, 138], may however result in normally-ON operations at elevated temperature. Improvements in terms of current densities (table 8) have been achieved with both normally-ON and normally-OFF JFET operating in bipolar mode, with the injection of minority carriers (electrons) in the p-type region. However, the bipolar conduction also increases the number of carriers in the channel and this would result in a slower turn OFF and a more complex gate driving technique.

Table 8. State-of-the-art parameters and key features for diamond BJTs, MESFETs and JFETs shown in figure 10.

Device	BJT	MESFET	JFET
Breakdown voltage	>100 V at T  =  300 K [140]	>2kV at T  =  300 K [133]	>600V at T  =  300 K [135]
		≈3kV at T  =  300 K for RB MESFET [134]
Current densitya	Not reported	≈2 mA mm−1 at T  =  500 K with VDS  =  −20 V VGS  =  0 V [142]	Max current (≈2 µA) at T  =  573 K with VDS  <    −10 V [138, 143]
	Max current ~µA at VEB  >  6 V [139]	≈0.14 mA mm−1 at T  =  300 K with VDS  =  −20 V VGS  =  0 V [142]	600 A cm−2 at T  =  500 K
		Max current  ≈30 mA at T  >  550 K [6]	40 A cm−2 at T  =  300 K with VDS  =  −1 V and Ig  =  0.2 µA/2nA (bipolar mode) [138, 143]
		≈0.1 mA mm−1 at VDS  =  −1 V VGS  =  0 V at T  =  600 K [132, 142]
			≈3.5k A cm−2 at T  =  500 K with VDS  =  −20 V and Ig  =  1 µA (bipolar mode) [143]
Notes	Need good doping control of both n-type and p-type layer	Radiation hardness even at high junction temperature	Bipolar mode operations and normally-OFF demonstrated
	Lifetime control is needed for high current gain	Easy fabrication process (only requires p-type doping)	Positive temperature coefficient of the BV
	Low BV	Good scaling of the BV with the drift layer length	Requires n+  doping
			HT operations improve the Ron_spec but the temperature can seriously affect the operation mode (normally-OFF becomes normally-ON).

^aThe reported current density for diamond lateral JFET is normalized with the cross-sectional area.

The recent progress in the n-type doping technology has also allowed the fabrication of bipolar junction transistors (BJTs) [139–141]. Indeed, early fabrication processes have failed to demonstrate the bipolar mode operation due to the high resistivity of the n-type base layer (around 10¹⁸ cm⁻³) and the low diffusion length of minority carriers (holes) in the base region. The introduction of the n+  layer has enabled both the hopping conductivity and the reduction of the series resistance due to the ohmic contact of the base. However, the scalability of these devices is highly limited due to the low diffusion length [140].

4.2.3. 2DHG-based FETs

The 2DHG formation near the hydrogen-terminated diamond surfaces provides an innovative way to obtain an almost zero activation energy hole channel. This effect, which was revealed in the early 1990s [144–147], was found to be useful for the fabrication of surface channel FETs [54]. In addition, the maximum measured channel mobility, typically around 100 cm² V⁻¹, s⁻¹ and the sheet hole density, which oscillates between 10¹² cm⁻² and 10¹⁴ cm⁻² (with NO₂ adsorption [148, 149]), are promising electrical properties for the next generation of diamond power devices [150].

Atomic layer deposition of Al₂O₃ has been proven to be a new way to uniformly induce the hole accumulation layer and improve the overall reliability and stability of the heterojunction field-effect transistors (HFETs) [148, 151]. Compared to the surface adsorbates, the insulating layer possesses some unoccupied orbitals or fixed negative charges, which are responsible for the formation of the 2DHG at the interface [152]. Lateral normally-ON HFET with a high BV (over 1.5 kV) and HT (>725 K) stability have been reported in the literature (table 9) [57, 153–158]. Lateral triple-gate HFETs, which allow carrier to flow in both lateral and planar directions, have illustrated higher current density and more promising downscaling scenarios compared to classic lateral HFETs [159].

Several solutions have also been implemented to avoid the formation of the 2DHG under the gate region and achieve the enhancement mode behavior. For example, Liu et al [154, 160] deposited a double high-k layer oxide to avoid the formation of unoccupied levels and remove the 2DHG from the gate region, while Kitayabashi et al [11] obtained the normally-OFF operations with the partial oxidation of the channel region with C–O bounds. Because the hole sheet created at the diamond interface is not based on piezo-polarization effects as in AlGaN/GaN interfaces, it can be formed in non-planar structure (i.e. vertical trenches), as has already been reported by Inaba et al and Oi et al [161, 162] (figure 11). Temperature dependence of the leakage current still remains a fundamental issue with HFETs due to the residual doping concentration in the bulk region and the lack of proper isolation. In situ annealing performed prior the oxide deposition of the hydrogenated diamond surface at ~675 K was found to be crucial to enhance long-term doping stability of HFETs fabricated on MoO₃ and V₂O₅, as reported in [163]. This evidence opens a promising route for the HT applications and possible future commercialization of diamond HFETs.

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Table 9. State-of-the-art parameters and key features for diamond lateral and vertical HFET depicted in figure 11.

Device	Lateral HFET	Vertical HFET
Breakdown voltage	>2 kV at T  =  300 K [11]	≈350 V at T  =  300 K [161, 162]
Current density	1.3 A mm−1 at T  =  300 K with VGS  =  −5 V and VDS  =  −12 V [164]	>0.2 A mm−1 at T  =  300 K and T  =  600 K with VDS  =  −50 V and VGS  =  −20 V [161]
	0.2 A mm−1 at T  =  300 K with VGS  =  −5V and VDS  =  −1 V [164]	<10 mA mm−1 for VDS  =  −1 V and VGS  =  −5 V [161]
Notes	Lateral current flow limits the scalability of the ON state resistance	Beneficial vertical current spreading only starts from the p+  layer
	BV scalability is limited	BV is limited
	Beneficial for RF applications [156, 165]	Complex fabrication process, which requires deep etching
	Normally-OFF has been demonstrated	n-type layer specifications are crucial to reduce vertical leakage current
	Fabricated with both poly- and monocrystalline diamond

4.2.4. Vacuum switches.

Hydrogen-terminated diamond interfaces are well known to exhibit a unique property renowned in the literature as NEA, already discussed in section 2.3.2. This feature is very attractive for the realization of electron emitters as, from a theoretical point of view, electrons excited from the valence band or injected from contacts into the conduction band could be efficiently emitted in vacuum from the surface without any increase of the device temperature [166–170].

Table 10. State-of-the-art parameters and key features for diamond vacuum switch illustrated in figure 12.

Device	Vacuum switch
Breakdown voltage	10 kV at T  =  300 K [167]
Current density	4 A cm−2 at VG  <  −20 V at T  =  300 K [169]
Notes	Unique device concept
	Maximum current ~mA
	Exploit the NEA of diamond
	Efficiency and output capacitance (Coss) need to be improved
	Gate drivers may result in non-conventional designs for power electronics

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Experiments have confirmed electron emission from diamond p–n and PIN diodes with an efficiency oscillating around 2%. A schematic representation of the diamond vacuum switch fabricated in [167, 170] is illustrated in figure 12 and table 10.

A fair comparison between 2DHG-based transistors and bulk-doped ones (deep depletion or inversion MOSFET, MESFET, JFET) is very important for the optimization of the current diamond FET topologies for the next generation of power devices. First, the R_{on_spec} versus BV dependence needs to be carefully analyzed for different operating temperatures. At RT, the high 2DHG concentration gives rise to a total resistivity for HFETs, which is much lower than diamond bulk FETs. Indeed, while bulk diamond FETs tend to exhibit a much higher bulk mobility, their carrier density is seriously affected by the incomplete ionization effect. Besides, while the HT effects are almost negligible on the R_{on_spec} of 2DHG channels, their impact on bulk diamond FETs is much more significant due the enhanced activation of dopants (figures 3(a) and 4). Figure 13 shows the structure of the compared devices in the case of depletion mode MOSFET, with the consequent expression for the specific ON state resistance R_{on_spec}. Equations (7) and (8) show the relationship between sheet resistance R_s, and hole mobility µ_2DHG and sheet concentration in 2DHG Nsheet_2DHG (equation (7)), and bulk hole mobility µ_Drift and concentration p _Drift and drift region thickness d_Drift. The values of µ_2DHG and Nsheet_2DHG are plotted in figure 3(b). The values and dependences of µ_Drift are plotted in figures 3(a) and 4. For both devices, equation (9) shows the relationship between the specific ON state resistance R_{on_spec}, the sheet resistance R_s and the drift region length L_Drift.

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {\rm 2DHG}\,{\rm lateral}:\quad \quad \quad \quad {{R}_{{\rm s}}}=\frac{1}{q\cdot {{\mu }_{{\rm 2DHG}}}\cdot {{N}_{{\rm Sheet2DHG}}}}\quad \quad [\Omega \,{{}^{-1}}]\nonumber \end{align} \tag{ 7 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle & {\rm Bulk}\,{\rm lateral}:{\rm assuming}\,{\rm a}\,\nonumber \\ & {\rm constant}\,{\rm current}\,{\rm density}\nonumber \\ & {}{\rm through}\,{\rm the}\,{\rm whole}\,{\rm drift}\,{\rm region}\,{\rm thickness}\quad \quad {{R}_{{\rm s}}}=\frac{1}{q\cdot {{\mu }_{{\rm Drift}}}\cdot {{d}_{{\rm Drift}}}\cdot {{p}_{{\rm Drift}}}}=\frac{\rho }{{{d}_{{\rm Drift}}}}\quad \quad [\Omega /{{}^{-1}}]\nonumber \end{align} \tag{ 8 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {\rm Lateral}\,{\rm devices}:\quad \quad \quad {{R}_{{\rm on }\_{\rm spec}}}={{R}_{{\rm s}}}\cdot L_{{\rm Drift}}^{{\rm 2}}.\nonumber \end{align} \tag{ 9 }$$

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Figure 14 shows the comparison of lateral bulk and lateral 2DHG devices, for 1 and 3 kV cases, at various temperatures. In these plots, only the drift region resistance is considered, incomplete ionization of boron and hole mobility dependence with doping and temperature is modeled [70], and bulk and 2DHG devices have the same L_Drift value (NPT condition as predicted by [171]). For bulk devices, the relationship between the hole concentration P_Drift and the boron concentration N_A0 was presented earlier in figure 2(a)). For 1 kV, the parameters of the drift region are L_Drift  =1.9 µm and the boron concentration N_A0 equal to 1.8  ×  10¹⁷cm⁻³. For 3 kV, the parameters of the drift region are L_Drift  =  10 µm and N_A0  =  1.9 10¹⁶ cm⁻³.

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Typically, lateral 2DHG will have a non-intentionally doped drift layer, which would result in a reduced peak electric field at the breakdown and a wider drift region, with a consequently higher R_{on_spec} (not considered here). The resistivity in lateral 2DHG is assumed to be independent of temperature, as evidenced by experimental reports in [172]. As one can note from figure 14, there is a minimum drift region thickness for which the lateral bulk devices will have a smaller R_{on_spec} than lateral 2DHG, depending on the BV and junction temperature. The R_{on_spec} for vertical devices is plotted at RT and 450 K in figures 1(a) and (b). This analysis must then be integrated into a wider investigation, considering additionally voltage threshold tuning, gate and drain leakages, stability and reliability.

The increase of the junction temperature, which can enhance the conductivity in diamond layers affected by the incomplete ionization of the dopants, poses some important questions about the specific leakage current mechanisms occurring in actual devices. Indeed, such leakage currents, which are typically higher for increased junction temperature, can lead the devices into premature breakdown phenomena. While the most significant degradation performance has been observed in all diamond devices (e.g. SBDs) with a substantial number of dislocations and non-epitaxial crystallites [173], different leakage mechanisms occur in each specific device.

Regarding diamond Schottky diodes, thermionic field-emission leakage current with barrier lowering has shown good agreement with experimental results even at elevated junction temperature [21, 96, 174]. On the other hand, analysis on diamond PIN diode reverse characteristics between 323 K  <  T  <  423 K have suggested that Poole–Frenkel emission dominates at high electric field, while hopping conduction is the dominant mechanism at low electric field [102, 175].

On the other hand, the leakage current of MOS-based devices typically depends on the number and nature of interfacial traps at the diamond/oxide interface [121]. Leakage current mechanism occurring in oxygen-terminated diamond/Al₂O₃/Al has been investigated by Pham et al [122]. They suggested a four-step mechanism responsible for the negative bias leakage current, which originates from the hole carriers accumulated at the interface and it involves trap-to-trap tunneling in the oxide and charge transfer with the interface states. Thermal annealing of the gate oxide has been proven to reduce leakage current values in diamond oxygen-terminated MOS-based devices. With such a thermal process, the gate leakage current value was reduced by up to  <nA/mm (100 nA mm⁻¹) with VGS  =  45 V and VDS  =  −175V at RT (T  =  500 K). To date, the same analysis has not been carried out yet for hydrogen-terminated devices.

Lateral FET devices such as MESFETs and JFETs also suffer from buffer-related leakage current, which usually increase at HT due to the enhanced activation. Such leakage mechanism is also present in lateral HFET in which also the unintentionally doped substrate can play a key role at elevated temperature and increase the overall leakage in the device. To date, only a few studies have been dedicated to leakage current in diamond FETs. The lack of proper isolation between individual devices can also contribute to leakage at high-voltage values. Reactive ion etching techniques can indeed enhance sidewall leakage and create shorts and techniques such as partial mesa etch are usually preferred.

Without field relief designs, the typical vertical peak electric field at breakdown in diamond devices is limited to 1–2.5 MV cm⁻¹ [6, 46, 91, 112]. Therefore, the use of field relief structures is required in order to improve the BV capability and also to suppress the detrimental effects of the device termination on the field-enhanced leakage current mechanisms.

For unipolar mode diamond devices such as SBDs, field plate structures (figure 15(a)) have been more often adopted in the literature [89, 90, 92, 176, 177]. Theoretical optimization for a single-layer field plate structure has been carried out by Ikeda et al [91], showing that for a BV reached at a maximum leakage current density of 10⁻⁴ A cm⁻², an optimum oxide thickness can be obtained for Al₂O₃ (~1.5 µm) and SiO₂(~0.9 µm). Experimental results on vertical diamond SBDs have illustrated both a reduction of the leakage current and an improvement of the BV by using 0.2 µm Al₂O₃ on top of a 10 µm p-type boron-doped layer [46].

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Ramp field plate oxides have been suggested to be one of the most effective ways to reduce the peak electric field in SBDs (figure 15(b)). Calibration of ramp field plate termination by means of TCAD simulation has been performed by Brezeanu et al [177] and shown to be an almost ideal BV (92% of efficiency).

Diamond Schottky diodes with floating metal rings (figure 15(c)) have also been manufactured by Driche et al [178] and their efficient reduction of the electrostatic potential crowding has been confirmed by EBIC measurement. The spacing between the different rings and the number of rings influence the peak electric field and the shape of the lateral depletion. Due to the high field gradients in diamond, the reduced spacing of such rings induces a high stress on fabrication and lithography.

In diamond SBDs, the increase of the leakage current based on thermionic field emission effects [173, 179] could be efficiently tackled with a double metal termination (high barrier (HB) and low barrier (LB)), as shown in figure 15(d). By ensuring an LB in the central area of the structure, while increasing it in the periphery of the structure (with metals such as Au or Pt), it is possible to contemporarily suppress the value of the OFF state current and avoid any increase of the threshold voltage.

The lack of an efficient n-type doping and the issues arising from the ion implantation have junction termination extensions (JTEs) that are less effective in diamond (figure 15(e)). Kubovic et al [180] did not observe any improvement after the 10 nm of n+  type nitrogen-doped layer, while Huang et al [181] tried to obtain the same effect through H+  ion implantation to increase the resistivity, reporting a BV of about 3.7 kV for a diamond SBD.

SIPOS terminations provide a more uniform distribution of the field at the expense of an increased surface ohmic leakage (figure 15(f)). This kind of termination technique has been experimentally demonstrated for diamond SBDs and MESFETs [182]. Mesa etching termination technique could also be adopted for diamond p–n junctions, as already suggested in [110, 183]. However, one has to note that the optimal drift region thickness in diamond is larger than 10 µm for BVs above 3 kV [171] (theoretical) and etching thick diamond is a difficult process as the whole drift region must be etched. There is also the possibility of sidewall leakage induced by defects during etching, usually performed by deep reactive-ion etching. These considerations currently limit the possibility of mesa termination in the context of high-voltage diamond devices.

Due to the novel nature of diamond devices, no dedicated packaging technique has been developed yet. A suggested package solution for efficient thermal dissipation and its equivalent spice DC thermal network for a diamond power semiconductor has been illustrated in figure 16. In the literature, only a few diamond devices have been packaged and tested in power circuits. MESFETs in [89] have been packaged on a typical metal-ceramic package where the device was bonded with Au and molded with a resin. In [9], vertical-type Schottky diodes have been packaged with a silicone-based resin, which has then been hermetically sealed by the stainless-steel cover.

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As introduced hereinbefore, due to incomplete ionization, the R_{on_spec} of diamond bulk devices has a negative temperature coefficient (NTC). Furthermore, as demonstrated experimentally in [10], the switching losses are not affected much by increased temperatures. As a consequence, the total losses of diamond bulk devices have an NTC up to a HT where the losses are minimized.

This important NTC modifies the design of the heatsink with diamond devices, where self-heating can be used to increase the junction temperature and to reduce losses at the same time. Consequently, the Rth_CA can be largely increased with diamond devices, leading at the same time to lower power losses and smaller and lighter heatsink.

Figure 17 shows the comparison for two diodes having the same BV (1.2 kV) and current rating (10 A), based either on diamond or 4H-SiC (commercially available SiC device: CPW4-1200-S010B from Wolfspeed). The device area for diamond and 4H-SiC are, respectively, 0.37 and 3.92 mm² [184]. In all thermal analyses, the temperature within each die is supposedly uniform and equal to the related junction temperature. The ambient temperature has been set to 300 K.

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The current flowing through the devices is 10 A, with a duty cycle of 50%. Consequently, the relationship between the required total case to ambient thermal resistance Rth_CA, the junction temperature T_j and the losses dissipated by the devices are defined by equation (10). Here, only conduction losses are taken into account, while neglecting the junction barrier height (only conduction losses due to the series resistance).

The diamond device is supposedly vertical, with a doping level of 1.2 · 10¹⁷ cm⁻³ and a drift region thickness of 2.5 µm, as proposed in [171] under the NPT condition. The dependence of Ron on temperature has been taken from incomplete ionization and doping and temperature dependence hole mobility for diamond (figures 3(a) and 4), whereas taken directly from the datasheet for SiC.

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {\rm Rt}{{{\rm h}}_{{\rm CA}}}\left({{T}_{{\rm j}}} \right)=\frac{{{T}_{{\rm j}}} ~ [{\rm K}]-{{T}_{{\rm a}}} ~ [{\rm K}]}{{\rm Ron}\left({{T}_{{\rm j}}} \right)\cdot {{I}^{2}}{\rm *}\delta }=\frac{{{T}_{{\rm j}}}\left[ {\rm K} \right]-300\,[{\rm K}]}{{\rm Ron}\left({{T}_{{\rm j}}} \right)\cdot 50\,[{{{\rm A}}^{2}}]}.\nonumber \end{align} \tag{ 10 }$$

As with other power devices with NTC coefficients, the thermal stability and current focusing possibility are serious issues. As an example, the parallelization of such devices can be challenging, especially when the diamond dies are poorly thermally coupled. Figure 18 introduces an example where two diamond Schottky diodes are parallelized, but have a 10% dispersion in R_{on_spec}, which could be due to process dispersion. In this analysis, the 10% dispersion in R_{on_spec} is modelled with different diode active areas and similar J(V) characteristics. The initial R_{on_spec} and its dependence on temperature is taken from an actual diamond device [94], exhibiting a similar behavior to figure 17(a). The load current is 10 A with a duty cycle of 50%.

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As a consequence of the different Ron (10%), most of the current is running through one diode (diode 2%, 90% of the load current) and the other is conducting only a small part of the total current (only 10%). There is a clear current focusing effect due to the separate thermal heatsink and the small 10% dispersion in Ron of both diodes. Increasing the Rth_CA value will lead to higher junction temperatures of each parallel diode and for the same operating point. However, the total current is more evenly shared between the two diodes, after an electro-thermal transient (figure 19). Using larger Rth_CA values is however not recommended to mitigate the characteristic dispersions between diodes, as it would lead to higher junction temperatures and limited surge current capabilities.

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The consequences of this simple example are that diamond devices must be thermally coupled in the best possible way and that specific thermal simulations must be investigated to optimize the paralleling of diamond devices and for diamond power modules. On the same diamond die, one can expect that active cells paralleling will not be an issue due to the highest thermal conductivity of diamond, albeit with further investigations still required.

Reliability is one of the main concerns in diamond devices. Indeed, as the future generation of diamond power circuits is supposed to be working in extreme temperature conditions and for high frequency and voltage at the same time, the requirements on the overall system stability are even more strict than the one for silicon. Time-dependent dielectric breakdown (TDDB) needs to be properly addressed (as in GaN) as the increase of the electric field in the structure due to the high-voltage ratings may lead to a time-dependent failure of the protective layers. High-frequency performance with fast dV/dt and dI/dt could be limited by stray inductances and capacitances with possible enhanced oscillations, which may result in malfunctions or delay in the turn ON/OFF. Moreover, appropriate gate driving techniques and the reduction of parasitics also need to be considered in the design of diamond devices.

P-type transistors and diodes are the most promising diamond devices for future commercialization. In particular, the absence of high-performance p-type FETs in the existing power electronics market could open a specific opportunity for diamond. As an example, the co-package integration of diamond FETs with other FETs based on GaN, β-Ga₂O₃, AlN and 4H-SiC could represent a powerful solution for providing a smart IC avoiding external gate drives and thus reducing the parasitic inductances of external interconnections [152, 185].

However, there exist some obstacles to overcome for diamond before this material can meet commercial expectations. Despite the fact that diamond devices would have lower total losses than other semiconductors, the power density losses are increased. Consequently, there is a higher stress on thermal spreader, accentuated by the higher junction temperatures of diamond devices. The system level benefits and challenges of diamond devices can be summarized as follows:

5.1.1. Benefits.

5.1.2. Challenges.

Diamond devices are usually small in size and therefore can conduct only low currents. From this perspective, parallelization becomes an essential technique for increasing the current flowing through diamond devices. Examples of diamond diode parallelization in a buck DC/DC converter have already been studied in [10] and also partially addressed in section 4.6. In [10], the diamond pseudo-vertical Schottky diodes were connected to a common anode and had isolated cathodes. A high-side commercially available Si MOSFET was implemented in the experimental setup for the double pulse test in order to match the requirement of current/voltage of the diodes under test. The presence of the Si MOSFET limited the maximum switching speed of the system together with the parasitics (i.e. capacitances and stray inductances). However, it is critical to have similar output capacitance between the high-side device (silicon transistor) and low-side device (diamond Schottky diodes in parallel). Coupling parallel diamond devices with high BV (>100 V or  >1 kV) and a very low current capability (<1 mA) on the high side with other power devices made of silicon, SiC or GaN on the low side, while maintaining similar output capacitance is very challenging. In [60], a high switching speed was observed (tens of V/ns) with reduced oscillations mainly due to the low value of the switching current and significantly high ON state resistances. Such a parallelization of diamond devices was also analyzed for an interleaved configuration, which eased the increase of switching frequency with benefits related to the output filter design and control bandwidth (figure 20). The interference between the diamond diodes integrated on the same chip highlighted the importance of device isolation.

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The interleaved setup may represent a promising configuration for the next generation of diamond converters with the on-chip integration of parallel p-type FETs on the same substrate. Besides, an asynchronous DC/DC buck converter could benefit from the addition of a diamond p-channel FET due to the simplified gate driving technique (for the high-side switch). However, unbalances between the different devices may impact negatively on the overall speed and current of the final converter, as already pointed out for diamond SBDs (section 4.5).

Bridge converters with an integrated diamond solution would ideally require n-type FETs to simplify the gate driving technique. Nonetheless, a smart on-chip integration of a gate driver for the low-side p-type diamond FETs could partially solve the issue arising from the absence of n-type diamond FETs. Finally, isolated p-type diamond converters made with only p-type FETs and diodes could offer a different solution to tackle the gate driving 'issues of bridge configurations and other converters' typologies.

With many factors impacting on the electro-thermal performance and different physical mechanisms involved in the electron–hole current transport, the optimal choice between unipolar and bipolar devices for power electronics applications needs to be carefully made [186, 187]. One of the most accurate approaches to follow is the one described by Morisette et al [186] for SiC diodes. This optimization is principally based on maximizing the available current density at a fixed BV and switching frequency (f). If one assumes that the package and cooling system cost between the two devices can be assumed identical, the only significant difference in cost is associated with the die. Therefore, higher current densities will allow for a reduced die area and lower cost for that specific device.

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In the analysis presented in this paragraph, a simple inductive load switching circuit is considered and the energy dissipated by the main switch (an FET such as a MOSFET/ insulated gate bipolar transistor (IGBT)) is assumed to be directly based on the charge stored in the diode.

Under these assumptions, the static (P_static) and dynamic (P_dynamic) power density components for a power diode can be written as shown in equations (11) and (12) [74]:

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{{\rm static}}}={{J}_{{\rm F}}}{{V}_{{\rm F}}}\delta +{{J}_{{\rm R}}}{{V}_{{\rm R}}}\left(1-\delta \right),\nonumber \end{align} \tag{ 11 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{{\rm dynamic}}}=f\left({{E}_{{\rm on}}}+{{E}_{{\rm of\,\!f}}} \right),\nonumber \end{align} \tag{ 12 }$$

where J_F is the current density in the ON state, V_F is the forward voltage drop, $\delta$ is the duty cycle (assumed equal to 0.5 in this study), J_R is the reverse current density, V_R is the reverse voltage (assumed equal to the BV in this simplified analysis), f  is the switching frequency, and E_on and E_off are the energies loss densities by the diode during the turn ON and turn OFF transient of the diode. In addition, V_F can be expressed as the sum of the built-in voltage (V_bi) and the specific ON state resistance of the diode (R_P) multiplied by the forward current density for the PIN diode. In the formula of equation (13), the built-in voltage (V_bi) is a function of the band gap (E_G), the impurity concentration of the P, P+  and N+  type layers, the density of states in the valence and conduction band and the operating temperature [34]. A different (but similar) expression holds for SBDs, as shown in equation (14) [34, 96]. In (14), η is the ideality factor of the diode (here assumed equal to 1), V_bn is the barrier height and A^* the Richardson constant (assumed equal to 88 A (cm² K²)⁻¹ from the matching with experimental diamond SBDs [96, 97]).

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{V}_{{\rm F(PIN)}}}={{J}_{{\rm F}}}{{R}_{{\rm P}}}({\rm PIN})+{{V}_{{\rm bi}}}(T,{{N}_{{\rm A0}}},{{N}_{{\rm D0}}}),\nonumber \end{align} \tag{ 13 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{V}_{{\rm F(SBD)}}}=&~{{J}_{{\rm F}}}{{R}_{{\rm P}}}({\rm SBD})+\eta {{V}_{{\rm bn}}}(T,{{N}_{{\rm A0}}},{{N}_{{\rm D0}}})\nonumber \\ & +\frac{\eta kT}{q}\ln \left(\frac{{{J}_{{\rm F}}}}{{{A}^{*}}{{T}^{2}}} \right)={{J}_{{\rm F}}}{{R}_{{\rm P}}}({\rm SBD})+{{V}_{{\rm bi}}}({\rm SBD}).\nonumber \end{align} \tag{ 14 }$$

Regarding the specific ON state resistance of the p region for the SBD (figure 21(a)), the absence of minority carriers results in the expression (15)—where p  is the active carrier concentration calculated by means of the incomplete ionization model and d(SBD) is the optimal punch-through thickness as in [171].

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{R}_{{\rm p}}}{\rm (SBD})=\frac{d({\rm SBD})}{qp{{u}_{{\rm p}}}}.\nonumber \end{align} \tag{ 15 }$$

Regarding the bipolar PIN diode (figure 21(b)), the specific ON state resistance can be expressed as in (16):

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{R}_{{\rm p}}}({\rm PIN})=\frac{d({\rm PIN})}{qp{{u}_{{\rm p}}}+\frac{({{u}_{{\rm p}}}+{{u}_{{\rm n}}}){{J}_{{\rm F}}}\tau }{d({\rm PIN})}},\nonumber \end{align} \tag{ 16 }$$

where d(PIN) is the optimum drift layer thickness and $\tau$ is the ambipolar lifetime.

Unlike in the SBD, the best set of coefficients (d(PIN), N_A0) cannot be obtained with a closed form optimization, and an iterative technique by means of TCAD simulations is therefore needed. For the purpose of this study, d(PIN) has been calculated by solving the ionization integral with the coefficients from [188, 189] and extracting the minimum thickness, which gives a specific BV for a fixed dopant concentration (N_A0) of 5  ×  10¹⁴ cm⁻³. This choice of the dopant concentration has been carried out to allow a good level of conductivity modulation in the p-type layer.

With the previous assumptions in mind, the charge density stored in the PIN diode (Qs) can be expressed as the product J_F * $~\tau$ and the energy density associated with the reverse recovery of the PIN diode during the turn OFF can be expressed by (17):

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{E}_{{\rm of\,\!f}}}({\rm PIN})=\tau {{J}_{{\rm F}}}{{V}_{{\rm R}}}.\nonumber \end{align} \tag{ 17 }$$

For the purpose of this study, E_on, which is the energy dissipated by the diode during its turn ON, has been neglected for both the Schottky and PIN diode. Furthermore, the E_off component of the diamond SBD has been neglected, as no significant stored charge needs to be removed from the p-type layer, which is only composed of majority carriers (holes in this specific example). Nonetheless, high switching frequencies (>100 kHz) could have an impact on the dynamic power dissipations with the flow of the displacement current in the diode. This component (P_disp) has been taken into account for both devices, as shown in equation (18) where ε is the dielectric permittivity of diamond, which has been assumed frequency independent.

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{{\rm disp}}}=\frac{f}{3}\sqrt{\frac{\varepsilon q{{N}_{{\rm A0}}}}{2}}{{\left({{V}_{{\rm F}}}+{{V}_{{\rm R}}} \right)}^{\frac{3}{2}}}.\nonumber \end{align} \tag{ 18 }$$

Bearing in mind all the previous assumptions, the total power dissipation (static and dynamic) for both devices can be expressed as in (19) and (20):

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{{\rm (SBD)}}}=& ({{J}_{{\rm F}}}{{V}_{{\rm bi}}}\left({\rm SBD} \right)+J_{{\rm F}}^{{\rm 2}}{{R}_{{\rm p}}}({\rm SBD}))~\delta \nonumber \\ & +{{J}_{{\rm R}}}{{V}_{{\rm R}}}\left(1-\delta \right)+{{P}_{{\rm disp}}}\left({\rm SBD} \right),\nonumber \end{align} \tag{ 19 }$$

$$\begin{align} \newcommand{\e}{{\rm e}} \displaystyle {{P}_{(PIN)}}=&({{J}_{{\rm F}}}{{V}_{{\rm bi}}}\left({\rm PIN} \right)+J_{{\rm F}}^{2}{{R}_{{\rm p}}}({\rm PIN}))~\delta \nonumber \\ & +{{J}_{{\rm R}}}{{V}_{{\rm R}}}\left(1-\delta \right)+f\tau {{J}_{{\rm F}}}{{V}_{{\rm R}}}+{{P}_{{\rm disp}}}\left({\rm PIN} \right).\nonumber \end{align} \tag{ 20 }$$

For the purpose of this study, the component J_R has been neglected in both formulas.

In detail, for the PIN diode, J_R is mainly due to the thermal generation-recombination process and can be ignored if one assumes a good quality of the material (low leakage current due to dislocations and defects). Regarding the SBD, such a component of the leakage current needs to be carefully considered as it can be significant for high electric field due to the thermionic field-emission process. For the purpose of this study, the maximum level of the leakage current for SBD has been fixed at 1 µA cm⁻² and the optimal ${{V}_{{\rm bn}}}$ has been extracted using the procedure illustrated in [96] at different operating temperatures. The optimal ${{V}_{{\rm bn}}}$ allows us to minimize the ON state voltage drop and at the same time to maintain the desired leakage current density value for a specific reverse voltage.

Moreover, the ambipolar lifetime value $\tau$ has been optimized in order to minimize the power density expressed in (18) by setting the first derivative of P_(PIN) equal to zero (figure 22). The optimal value of the lifetime ($\tau$_opt) emerges from the trade-off between the static power dissipation, which is reduced for high values of lifetime thanks to the conductivity modulation effect and the increased dynamic power dissipation, which increases for larger stored charge (Q_s).

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Once the set of optimal parameters has been extracted, the procedure can be concluded by fixing a value for the maximum power density and by maximizing the J_F for each device by using formulas (17) and (18). The value of the maximum allowable power density typically depends upon the package capability (especially on the thermal spreader design) and it oscillates between 50–300W cm⁻² for commercial devices. In this section, this value has been chosen to be 500 W cm⁻², a value which is justified by the increased thermal capability of diamond devices.

At RT and for low BV (<4 kV), the current density for SBDs is higher than PIN diode and the SBD is the preferred device for the whole range of frequencies (figure 23). As the BV increases, the 'optimized' conductivity modulation occurring in the PIN diode allows for reduced power losses. For ultra-high BV (>20 kV) and for switching frequencies  >10 kHz, the SBD again becomes superior to the PIN diode. At higher junction temperature (T  =  450 K) the trade-off between the two devices is modified due to the dependence of the leakage current upon the temperature, carrier activation, carrier mobility, density of states, etc, which modify the set of optimal parameters for the analysis. The voltage versus frequency area in which the SBD displays higher current density compared to the SBD is widened and the PIN diode becomes a better choice only for reverse voltage  >7 kV and f   <  10 kHz.

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In this section, a comparison between the R_{on_spec}, total semiconductor losses, junction temperature, heatsink volume, semiconductor active area, current density and power loss density of bulk diamond devices against GaN on GaN and 4H-SiC power devices is provided. In this comparative analysis, only unipolar devices will be considered. Above 3 and at 10 kV in particular, vertical GaN devices on bulk GaN substrates will be considered for this study. 4H-SiC vertical bulk devices, already demonstrated to withstand up to 27 kV [190], will be considered in this analysis.

The models and basic assumptions for diamond devices are based on those used in the previous sections, including incomplete ionization, simplified switching loss model, NPT vertical drift region, doping and temperature-dependent mobility, impact ionization coefficients for BV. The parasitic Coss and the ON state resistance are assumed to be due only to the drift region. For the heatsink volume, natural convection is considered with a volumetric resistance of 500 cm³ K W⁻¹ [191].

This value typically overestimates the heatsink volume, whereas forced air solutions can reduce the heatsink volume by a factor of 5–10. However, this assumption will allow a quantitative benchmark on diamond devices versus other materials. The ambient temperature will be set to 300 K (tables 12 and 13).

For a 10 kV BV, the drift region of bulk diamond, bulk GaN and 4H-SiC devices are based on the parameters shown in table 11. The switched voltage and current are 6 kV and 10 A, respectively. The duty cycle is set at 0.5 and the switching frequency at 20 kHz (note that this is a very high switching frequency for such high-voltage power devices).

The comparison between vertical unipolar bulk diamond, GaN on GaN substrates and 4H-SiC is presented in tables 12 and 13 and figures 24–27. Key elements can be highlighted.

• Even at the 'low' temperature of 400 K, diamond power devices have 29% less total losses and heatsink volume than GaN, requiring 22% less active area. With diamond, the current density is around 42 A cm⁻², and the loss density is under 130 W cm⁻² at 20 kHz, albeit 17% more than GaN. The analysis is similar with 4H-SiC, where diamond has 11% less total losses and heatsink volume, with 21% more current density.
• At 450 K, diamond devices have 33% higher current density, 28% less losses and heatsink volume than 4H-SiC at the same temperature. Diamond devices have 7% higher power loss density than 4H-SiC. Compared to GaN at the same temperature, diamond devices have 20% higher current density, 19% less losses and heatsink volume.

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Increased junction temperature of 500 K will allow diamond devices to gain benefit from the increased dopant activation (no compensation is assumed here). At this junction temperature, diamond devices outperform both SiC and GaN at the same junction temperature. The benefits of diamond devices are even higher if compared with GaN and SiC operating at lower junction temperature. In detail:

• Diamond devices at 500 K would require 58% less heatsink volume than GaN operating at 400 K, with at least 17% less losses and half the active area. The current density in diamond at 500 K is approximately 40% higher than GaN at 400K.
• Diamond devices at 500 K would require 40% heatsink volume of that of 4H-SiC devices operating at 400 K, with 20% less losses and 25% less active area. The current density in diamond at 500 K is 32% higher than that of 4H-SiC devices at 400 K.

For the 10 kV range, diamond devices are expected to have smaller losses, heatsink volume and active area than other materials. Diamond is still superior to 4H-SiC even at 400 K, although the gap in the performance is significantly amplified above 450 K.

It is also possible that the performances of diamond devices are still underestimated. Indeed, improvements in the crystal structure could result in larger critical electric fields (above what has currently been measured). In that case, the impact ionization coefficients would need to be updated particularly if thick and low doping drift regions are considered for the 10 kV+  range of rated breakdowns. To some extent, this is also the case for bulk GaN above 3 kV and 400 K, though it is less likely to see a significant difference.

In order to compare power devices at an operating temperature close to RT, table 14 shows the system level performances. Please note that industrial ambient temperatures can be as high as 358 K, and even up to 398 K (e.g. automotive applications). Hence, table 14 also shows the comparison between diamond, SiC and GaN, for the same 10 K difference between the junction temperature and the ambient temperature, but with an ambient temperature of 400 K. By comparing tables 12–14, one can also note the impact of lower junction temperatures on the heatsink volume and the total losses.

As shown in table 14, bulk diamond devices are not well suited for an operation at T_j  ≈  300 K. This is no longer the case when the ambient temperature is increased. Moreover, if a large temperature gradient between the junction temperature and RT of 300 K is desired to reduce the heatsink volume or to increase the current rating, then diamond has significant system-level benefits, as presented in tables 12 and 13.

The main challenges for diamond power devices can be organized into five categories: (i) material, (ii) devices, (iii) packaging, (iv) reliability and (v) integration. Their current status and future prospective are shown in table 15.

6.1.1. Material.

6.1.2. Devices.

6.1.3. Packaging.

6.1.4. Reliability.

6.1.5. Integration.

Wafer integration of parasitic and smart gate driving circuits will enable low-volume diamond converters and improve dV/dt and the dI/dt for the packaged devices. The smart integration of diamond and other WBG/UWBG semiconductors (figure 28) could represent one of the possible applications of diamond p-type FETs in a monolithic high-speed converter.

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The remarkable advantages of diamond for power electronics have been accompanied by drawbacks and limiting factors. While some of the challenges, which for years have hampered the development of this material have been addressed, other questions still remain unanswered. With the principal aim of reviewing the diamond technology and modelling the most promising devices, this topical review has provided a new thorough overview of the current state-of-the-art and future trends. Significant effort, especially in the last decade, has resulted in a class of new diamond power devices, which have the potential to find their place in the diverse power electronics market in the future. The comprehensive analysis conducted in this paper has however demonstrated that the superior potential of diamond is mainly restricted for high junction temperatures (>450 K), medium-high frequency (>20 kHz) and high-voltage (>3 kV) applications when compared to 4H-SiC and GaN commercial alternatives. Besides, the results illustrated in this work have pointed out the significant thermal management issues that need to be addressed to allow for the efficient parallelization of multiple diamond devices with an NTC.