High performance top-gated multilayer WSe₂ field effect transistors

The outstanding electronic transport properties of graphene, including extremely high carrier mobilities, have generated significant interest in graphene based nanoelectronics [1–3]. With the successful exfoliation of graphene and the demonstration of the remarkable electronic properties, considerable research has been carried out on both large-area synthesis of graphene and its potential device applications [4–6]. Despite its remarkable electronic properties, the lack of a sizable band gap hinders the use of graphene in many applications. Alternatively, semiconducting layered transition metal dichalcogenides (TMD) can circumvent this issue, thereby paving the way for the realization of digital logic circuits utilizing 2D layered materials. Moreover, it has been shown that the band structure of some TMD materials exhibit a unique indirect-to-direct band gap transition from bulk to single layer structure [7, 8]. For example, bulk WSe₂ is an indirect band gap (∼1.2 eV) semiconductor, whereas its monolayer exhibits a direct band gap of ∼1.65 eV [9, 10]. The direct band gap of single layer TMDs can offer exciting opportunities for potential applications in both digital electronics and optoelectronic devices [11–13]. Furthermore, WSe₂ is a very promising material due to the fact that n-type, p-type, and ambipolar carrier transport can be achieved by thickness modulation and electrode engineering [14–16], which is challenging for other TMD materials, like MoS₂, due to strong Fermi layer pinning effects [17]. To date, most of the high performance WSe₂ field effect transistors (FETs) have been demonstrated in common bottom-gated configuration due to the difficulty of synthesizing high-quality top-gated dielectrics directly on the WSe₂ channel surface due to the absence of dangling bonds on its surface [18, 19]. For practical device applications, top-gated WSe₂ FETs with high-k dielectrics are highly desirable. The common bottom-gated FET architecture is not compatible with integrated circuit technology as it cannot individually address each device. Additionally, it is reported both theoretically and experimentally that, high k-dielectrics in top-gated configurations are essential to suppress coulomb impurity scattering in TMD channels for low-power device operation with enhanced gate coupling, high carrier mobility, and large saturation current [20–22]. Deposition of sub-10 nm uniform films of high-k dielectrics have been well-established via the ALD techniques [23–25]; however, the conformal deposition of high k-dielectrics on TMD surfaces remain a challenge since there are insufficient dangling bonds or reactive sites to catalyze the layer-by-layer growth on the channel. In general, there are limited studies performed to improve the coverage of high-quality ALD dielectrics deposition directly on TMD surface. Various approaches have been proposed to achieve high quality, low-leakage oxide thin films; TMD surface functionalization [26, 27], metal/metal oxide seed layer deposition [16, 28, 29], self-assembled monolayers [25, 30], UV/Ozone plasma treatment [19, 31, 32], to name a few. Most of the ALD techniques employed to deposit high k-dielectric on 2D materials surface to date, are thermal (H₂O precursor) ALD processes. Very few studies have reported plasma (O₂ precursor) assisted ALD processes on 2D materials and to our knowledge have been limited to graphene FET devices [33, 34]. The use of a plasma mediated ALD process, allows for more freedom in processing conditions and for a wider range of material properties compared with the conventional thermally driven ALD process [35]. Additionally, relatively faster deposition rate, fewer contaminates, constant growth rate at lower temperature and smaller nucleation delay are compelling reasons for employing plasma ALD for depositing high quality dielectric films on TMDs surface. However, a comprehensive study of the effects of the plasma and the studies for mitigating the plasma induced doping/defect are lacking.

In this work, we demonstrate high performance top-gated WSe₂ FETs via a remote plasma assisted ALD process. A two-step remote plasma assisted ALD process with an ultrathin Ti buffer/seed layer is employed for the first time to achieve a high-quality, low-leakage Al₂O₃ top gate dielectric layer on clean WSe₂ surface. An excellent top-gated device performance with current on–off ratios exceeding 10⁶ and field effect hole mobility around 70 cm² V⁻¹ s⁻¹ at room temperature are achieved.

ALD growth of Al₂O₃

Device fabrication and electrical measurements

Prior to the fabrication and characterization of top-gated WSe₂ FETs via a two-stop remote plasma assisted ALD process describe herein, we characterized the bottom-gated WSe₂ FETs. Figure 1(a) shows a cross-sectional schematic of the bottom-gated few-layer WSe₂ FETs with a 290 nm thermal oxide (SiO₂) gate insulator. An AFM micrograph of one of the exfoliated WSe₂ flakes is shown in figure 1(b). Figure 1(c) shows the height profile along the white line shown in figure 1(b), indicating the two different thicknesses of the flake, namely, ∼2.8 nm (4 layer) and ∼4.3 nm (6 layer). WSe₂ is a very promising material due to the fact that the carrier transport properties can be tuned via thickness modulation and electrode engineering. In this study, various electrode materials and WSe₂ layer thicknesses were studied. The original intent of this work was to create an inverter device on a single flake by selecting appropriate electrode materials and WSe₂ thickness to create both n and p-type transistors. Although an integrated inverter was not achieved, interesting devices characteristics for a variety of device structures were elucidated. Consistent with prior work demonstrating various carrier type control using a nickel electrode [14], we recently demonstrated similar behavior for Cr–Au contacts and Pd contacts due to band offset [39]. Thus for reference, Ti–Au contacts are consistently ambipolar, Pd has a high work function and thus promote hole injection into the valence band for p-type behavior, whereas Cr promotes electron conduction and n-type behavior for thicker flakes (<3 nm) transitions to ambipolar (4 nm) and n-type (>5 nm) due to band alignment to the changing bandgap with WSe₂ thickness. The ambipolar behavior exhibited with Ti–Au electrodes is attributed to the formation of TiO_x at the Ti–WSe₂ interface, which has been demonstrated to occur even during high-vacuum deposition [40]. Thin oxide formation at metal–semiconductor interfaces can induce the formation of dipoles which can be used to tune Schottky barrier height, and transport behavior cannot be predicted by simple band offset.

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The part of the flake with 4 layers is metallized with Pd contacts, while the part of the flake with 6 layers is metallized with Ti/Au contacts. The optical micrograph of the fabricated bottom gated WSe₂ FET device is shown in the inset of figure 1(c). Figure 1(d) shows the typical bottom SiO₂ gate transfer characteristic (I_DS–V_GS) curves for a WSe₂ FET with Pd contacts at three different source-drain voltages, i.e. V_DS = 0.1, 0.6, 1.1 V. Consistent with the high work function of Pd, the measured source-drain current increases with an increase in the negative gate bias voltage, indicating a clear p-type carrier transport. This results in promising current on–off ratios as high as 10⁶ and field effect linear mobility of 20 cm² V⁻¹ s⁻¹. Figure 1(e) shows the I_DS–V_GS curves for the 6 layer WSe₂ FET with Ti/Au contacts. As expected, ambipolar carrier transport is observed. The I_DS increase with increasing gate bias both in positive and negative directions, leads to an on–off ratio in excess of 10⁶ in both the electron and hole transport regimes. The field effect linear electron and hole mobility values of 11 cm² V⁻¹ s⁻¹ and 10 cm² V⁻¹ s⁻¹, respectively, have been extracted from the measured transfer curve in figure 1(e). The field effect mobility is extracted from the linear region of the device transfer characteristics by the following equation:

$$\begin{eqnarray}&&\mu =\left(\displaystyle \frac{L}{W\times C\times {V}_{{\rm{D}}{\rm{C}}}\,}\right)\displaystyle \frac{{\rm{d}}{I}_{{\rm{D}}{\rm{S}}}}{{\rm{d}}{V}_{{\rm{G}}{\rm{S}}}},\end{eqnarray} \tag{ 1 }$$

where L and W are the channel length and width, and C is the specific capacitance of the gate dielectric.

The deposition of high-quality, low-leakage, high k-dielectrics on WSe₂ remains challenging since there are insufficient dangling bonds or nucleation sites on the WSe₂ channel. There are limited studies performed to deposit high-quality ALD dielectrics on the surface of WSe₂. Surface functionalization of TMD channels with an oxygen/hydrogen plasma treatment was recently demonstrated to promote the reactivity of TMD surfaces with ALD precursors [19, 41]; however no electrical data was presented. We observed a significant change in the electrical transport properties of few-layer WSe₂ FETs due to a H₂ plasma surface treatment prior to the top gate dielectric deposition. Gate control of few-layer WSe₂ devices are deteriorated after 1 min of hydrogen plasma treatment prior to top gate dielectric deposition, see figure 2(b). Not surprisingly, the corresponding top gate device measurement reveals no gate modulation, figure 2(c). This can be attributed to the formation of excessive selenium vacancies, thereby deteriorating semiconductor properties of the WSe₂ channel. Similar loss in gate control on few-layer WSe₂ FETs device have been observed in our previous report [38, 42], by irradiation the device with a focused He ion dose in excess of 1 × 10¹⁶ ions cm⁻². On the other hand, a short (∼1 min) oxygen plasma surface treatment under similar plasma conditions results in a significant change in transport properties as well (initial n-type behavior is changed to p-type carrier transport). Various groups have reported an island overgrowth of high k-dielectric onto exfoliated TMD crystals. McDonnell et al [43] have reported that ALD on MoS₂ bulk material is not uniform. No covalent bonding between the HfO₂ and MoS₂ was detected. Furthermore, Park et al [26] have reported that, 5.5 nm deep pinholes were present in 10 nm Al₂O₃ films deposited onto WSe₂ with diameters of 100–500 nm and a root-mean-square surface roughness of 3.6 nm. In contrast to these observations, we observed the uniform deposition of Al₂O₃ on WSe₂ with a two-step remote plasma assisted ALD process reported herein. Figure 3(a) shows an AFM image of a 30 nm ALD Al₂O₃ layer deposited on a pristine WSe₂ surface. The line profile shown in figure 3(b), suggests conformal deposition of the Al₂O₃ film without noticeable pine-hole regions and with marginal surface roughness. It is worth noting that a relatively low deposition temperature of 50 °C is employed for the first 10 cycles ALD (∼2 nm film) prior to rest of the film deposition for the uniform surface coverage. An additional AFM micrograph of a 10 nm Al₂O₃ film deposited on a WSe₂ flake can be found in the supporting information file figure S1 is available online at stacks.iop.org/NANO/28/475202/mmedia. Despite having the conformal ALD deposition on the WSe₂ channel via the two-step remote plasma assisted ALD process, the electrical transport properties of the WSe₂ FET device are significantly deteriorated (see supporting information file figure S2). The initial preferential n-type transport of the few-layer WSe₂ FET with Cr/Au contacts, as revealed from the back gate measurement, is noticeably changed. The top gate measurement reveals a slight p-type doping with very weak gate control. In order to deposit a high quality conformal Al₂O₃ gate dielectric without a significant change in structural and electrical properties of the WSe₂, we introduce an ultrathin Ti buffer layer prior to the ALD process. Approximately ∼1 nm of Ti is deposited via electron beam evaporation on clean WSe₂ surface prior to ALD process to minimize the unwanted doping or disorder introduced in the material during the O₂ plasma. Figures 3(c) and (d) plots the normalized Raman spectra of few-layer (5 layers) WSe₂ flakes before and after the ALD Al₂O₃ deposition with and without a Ti buffer layer. There is little change in the Raman spectra between the pristine WSe₂ and the WSe₂ with an Al₂O₃ dielectric. This suggests that much of the structural integrity of the material is maintained after Al₂O₃ deposition. Figure 3(d) plots the A_1g and ${{{E}}^{1}}_{2{\rm{g}}}$ Raman peaks (∼246 cm⁻¹) which are nearly degenerate in WSe₂. The 2LA(M) Raman peak is also shown at 256 cm⁻¹ [44]. Enhancement in the 2LA(M) mode is associated with disorder and defects introduced into the lattice [38, 45]. There is a clear rise in the 2LA(M) peak after Al₂O₃ deposition, however, the WSe₂ without the Ti buffer layer experiences the greatest enhancement in peak intensity. This indicates that the Ti buffer layer helps minimize defect generation during Al₂O₃ ALD deposition in comparison to the ALD process without a buffer layer. The Raman data clearly demonstrates that the Ti buffer layer is critical at minimizing damage to the WSe₂ layer during the plasma ALD process (figure 3(d)).

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Top-gated FETs were fabricated by depositing the 1 nm Ti buffer layer and 30 nm ALD Al₂O₃ on exfoliated few-layer WSe₂ channels as discussed earlier and illustrated in the schematic in figure 4(a). The optical image of a fabricated top-gate device, which was previously studied in bottom gate configuration (figure 1(b)) is shown in figure 4(b). Two devices with different metal contacts, namely, Pd and Ti/Au were fabricated on the same WSe₂ flake which has slightly different thickness. Top gate electrodes (5 nm Ti/30 nm Au) were fabricated after the ALD top gate dielectric deposition via EBL followed by electron-beam evaporation. Complete gate-to-source or drain overlapping is used to minimize parasitic resistance. Figures 4(c) and (d) show typical output (c), and transfer (d) characteristics of the top-gated WSe₂ FETs with Pd source-drain contacts. As observed previously in the bottom-gate configuration, the top-gated device also shows p-type carrier transport, which indicates that the Ti buffer layer successfully prevented damage or doping of the WSe₂ during dielectric deposition. The output characteristic in figure 4(c) shows that I_DS increases linearly with V_DS at lower values of V_DS and saturates at higher values of V_DS. The linear regime can be attributed to the good Ohmic contacts between the Pd electrodes and the few-layer (∼2.8 nm) WSe₂ channel. The pinch-off and I_DS saturation suggest that the carrier transport is completely controlled by the applied top-gate bias voltage.

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The measured transfer characteristics (figure 4(d)) demonstrate the ability to modulate the resistance of the WSe₂ channel by changing the top-gate voltage, yielding a current on/off current ratio exceeding 10⁶. The corresponding gate leakage current curves are also plotted in the same graph. The maximum leakage current density observed is below 10 pA cm^–2, indicating that a high-quality Al₂O₃ dielectric layer was deposited by the Ti-buffer layer and two-step plasma assisted ALD process. More than two orders of magnitude higher gate leakage current is observed for a device fabricated by depositing the Al₂O₃ gate dielectric layer in one step at 150 °C (see supporting information file figure S3). Furthermore, the initial low temperature (50 °C) ALD process is equally important to minimize the coalescence/dewetting of the buffer layer which degrades the device performance. Figure 4(e) shows the top-gated transfer characteristics of a few-layer (∼4.3 nm) WSe₂ FET with Ti/Au metal contacts at different source-drain voltages (V_DS). The drain current (I_DS) increases with increasing negative V_GS, and an insulating behavior is observed at or around zero gate bias. Current modulation is also observed for positive gate voltage, indicating the ambipolar carrier transport in the WSe₂ FET. A current on/off ratio in excess of 10⁷ and a high field effect hole mobility of ∼70 cm² V^–1 s^–1 were obtained. Furthermore, a clear subthreshold as observed in the transfer characteristic curve (figure 4(c)) along with a high current on/off ratio over 10⁷ and no obvious change in Raman spectra (figure 4) demonstrate that the integrity of the WSe₂ crystal is maintained during the plasma assisted ALD process. The intrinsic nature of WSe₂ is also evident from its insulating state at zero gate bias, indicating no intentional doping during the device processing.

In summary, a scalable remote plasma assisted ALD process for depositing high quality, low leakage Al₂O₃ gate dielectric on WSe₂ is reported for the first time. A two-step plasma assisted ALD deposition with an ultra-thin (∼1 nm) Ti buffer layer is employed for the deposition of conformal dielectric films on WSe₂ channels without noticeable pinholes, as shown by AFM imaging. The Ti buffer layer reduces disorder/defects in the material induced by the ALD process. Utilizing the described ALD deposition schemes, the fabricated top gated device exhibits high field effect carrier mobility, up to 70.0 cm² V^–1 s^–1, at room temperature and a large on/off current ratio exceeding 10⁶. The described top-gated WSe₂ FETs with impressive performance opens the roadmap for practical applications in integrated circuits.

PDR and MGS acknowledge support by US Department of Energy (DOE) under Grant No. DOE DE-SC0002136. PRP and DM acknowledge funding by the Gordon and Betty Moore Foundation's EPiQS Initiative through Grant GBMF4416. TZW acknowledges support US Department of Energy (DOE), Office of Basic Energy Sciences (BES), Materials Sciences and Engineering Division. The authors acknowledge that the device synthesis, Raman mapping were conducted at the Center for Nanophase Materials Sciences, which is a DOE Office of Science User Facility.

Competing financial interests

The authors declare no competing financial interests.

PRP, MGS, and ANH fabricated WSe₂ devices. PRP and DPB developed the atomic layer deposition recipe to create top-gated devices. PRP, KX, and AO characterized the electrical properties of the devices. PRP and MGS collected Raman spectra. ATW and TZW conducted AFM measurements of WSe₂. DGM synthesized the WSe₂. PRP and PDR conceived the experiments. PRP and MGS wrote the manuscript. All authors contributed to the analysis of data and revision of the manuscript.