The Schottky barrier transistor in emerging electronic devices

When a metal with work function ϕ_m is placed into intimate contact with a semiconductor with an electron affinity χ and Fermi level position ϕ_n below the conduction band, a net charge transfer occurs at the interface. An ideal theory for understanding these junctions, due to Mott and Schottky, is depicted in the energy band diagram in figure 1 for ϕ_m > χ + ϕ_n. An abrupt barrier, called the SB, arises at the MSJ due to the delta function of charge at the metallic interface. A charge depleted region that extends into the semiconductor also forms. In comparison with a p–n junction, where there is a depletion region on both sides of the interface, the SB allows for a much smaller space-charge region. SBMOSFETs are therefore advantageous for avoiding the merging of the depletion widths, which results in short-channel effects in reduced-dimension MOSFETs.

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The standard ideal description of MSJs assumes that (a) a maximum electric field occurs in the semiconductor, very close to the interface (due to image charge lowering) [13], (b) the only charges involved in the semiconductor are the donor impurities with concentration N_D, and (c) the space charge region is confined to a depletion zone, delimited by width W_D. Solving the Poisson equation we find

$$\begin{eqnarray}&&{W}_{D}=\sqrt{\displaystyle \frac{2{\epsilon }_{0}{\epsilon }_{{\rm{s}}}}{{{qN}}_{{\rm{D}}}}\left({\phi }_{\mathrm{bi}}-V-\displaystyle \frac{{k}_{{\rm{B}}}T}{q}\right)},\end{eqnarray} \tag{ 1 }$$

where _s is the dielectric constant of semiconductor, k_B is the Boltzmann constant, T is the temperature in Kelvin, V is the applied voltage, and ϕ_bi is the band bending in the semiconductor, known as the built-in potential. The length of the depletion region decreases with increasing doping concentration, which in general is limited by the solid solubility limit of the particular dopant. Note, however, that advanced techniques such as gas immersion laser doping [14] can overcome this limitation and are an important area of ongoing research.

Image charge lowering plays a role in the electrostatics during electron transport and becomes increasingly important in reduced-dimensional devices. As depicted in figure 2, this lowering is the result of the reduced field at the interface from the electrostatic attraction of a negative charge moving towards it. The resultant image charge lowers the barrier by

$$\begin{eqnarray}&&{\rm{\Delta }}\phi =\sqrt{\displaystyle \frac{{qE}}{4\pi {\epsilon }_{s}}},\end{eqnarray} \tag{ 2 }$$

where E is the externally applied electric field across the metal/semiconductor interface.

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Although this ideal theory is taught in semiconductor physics classes, we know from extensive research that the observed barrier height is rarely the one obtained from this analysis. While larger work-function metals do tend to have larger barrier heights, the dependence is much weaker than expected. The lack of correlation between the barrier height and the work-function is often attributed generically to 'Fermi-level pinning', covering a wide variety of different effects, including inhomogeneities at the junction, surface states at the interface due to either defects or to metal induced states, or chemical bonding at the interface [15]. Many of these models have similar dependencies with temperature and voltage and it is therefore difficult to disentangle the origin of the deviations of the barrier height without additional structural characterization techniques or different experimental conditions for the formation of the SB. Nevertheless, enormous progress in understanding has been achieved, as described in two excellent review articles [15, 16]. This progress originates from three significant advances: (1) the realization of epitaxial MSJs using molecular-beam epitaxy resulting in inhomogeneity-free interfaces, (2) the advent of scanning probe technologies allowing electrical measurements of nano-scale junctions, and (3) the development of powerful computers enabling first-principles ab initio calculations. This knowledge now makes it possible to understand and engineer the SB to a high degree of precision. For simulations and after an eventual optimization of the experimental devices, the Schottky barrier height (SBH) can be considered a parameter obtained from measurements. The mostly widely explored MSJs involve silicon/metallic silicon alloys, known as silicides, because of their wide industrial use in CMOS technology. These investigations have allowed thorough investigations of Si SBMOSFET devices.

Understanding the SB formation in more novel materials is an important subject of current research. An excellent review on the nature of contacts with one- and two-dimensional materials can be found in [17], while more recent reviews focused on two-dimensional materials can be found in [18–20]. Understanding the image charge lowering in bounded geometries [21] and the variation of the SB height in nanowire geometries have been explored by Calahorra et al [22], and measurements of barrier heights on Si nanowires using photoemission have been carried out by Yoon et al [23].

Electron transport in rectifying MSJs can be broadly grouped into 3 limiting transport mechanisms [5, 24]: (1) transport over the barrier, (2) tunneling through the barrier including direct, thermal- and trap-assisted tunneling, and (3) mechanisms occurring just adjacent to the barrier, such as diffusion and recombination. The overall current is modeled by a combination of these processes. Room temperature transport processes at the SB junctions that are used for transistors are most typically fully described by transport over the barrier via thermionic emission (TE), and direct/thermal assisted tunneling through the barrier [9], which are therefore the focus of this section.

The large majority of treatments of the current transport in SB diodes use semi-classical approximations. For TE and diffusion transport the basic equations can be rigorously derived from the Boltzmann transport equation [25], which provides a complete description of the distribution function. This formalism assumes that the band structure can be included into an effective mass and that the potential due to the applied field is small and does not vary rapidly in space.

The thermionic theory, proposed by Bethe [26] in 1942, describes how carriers with energies larger than q ϕ_Bn or q ϕ_Bp overcome the SB and contribute to electron transport. The total current is the sum of the two current densities that flow from the metal to the semiconductor and from the semiconductor to the metal. The current density is found by integrating over the concentration of electrons with velocities v_x in the transport direction and sufficient energy to overcome the barrier. In this classical calculation, the velocity is isotropic and given by a Maxwellian distribution with band structure taken into account via an effective mass m*. The sum of both current contributions for electrons is given by [13, 27–29]

$$\begin{eqnarray}&&{J}_{n}={J}_{\mathrm{TE}}\left[\exp \left(\displaystyle \frac{{qV}}{{k}_{{\rm{B}}}T}\right)-1\right],\end{eqnarray} \tag{ 3 }$$

where

$$\begin{eqnarray}&&{J}_{\mathrm{TE}}={A}^{* }{T}^{2}\exp \left(-\displaystyle \frac{q{\phi }_{\mathrm{Bn}0}}{{k}_{{\rm{B}}}T}\right).\end{eqnarray} \tag{ 4 }$$

Here ϕ_Bn0 denotes the intrinsic barrier height and

$$\begin{eqnarray}&&{A}^{* }\equiv \displaystyle \frac{4\pi {{qm}}^{* }{k}_{{\rm{B}}}^{2}}{{h}^{3}}\end{eqnarray} \tag{ 5 }$$

is the effective Richardson constant with h the Planck constant and m^* the effective mass. In this approximation quantum-mechanical reflections and optical-phonon scattering have been neglected, but detailed research has shown how to include these effects [28, 30] and subsequently how to include them in a modified effective Richardson constant. In silicon, A^* = 120 A cm⁻² K⁻² for electrons and 40 A cm⁻² K⁻² for holes. Other descriptions of transport over the barrier can include diffusion theory [5], which becomes important for materials with a small density of states. Image-force lowering must also be included, where the resulting barrier height ϕ_Bn0 for electrons from equation (4) is reduced by Δϕ from equation (2) [5]. The effective mass in the prefactor of this equation results in lower thermionic field emission for materials like Ge and GaAs.

Typical treatments of quantum mechanical tunneling in SB devices follow the method first considered by Bardeen [31], originally developed to explain tunneling in superconducting electrodes separated by a thin oxide. It was later extended by Harrison [32] to include regions of varying band structure. This approach solves the Schrödinger equation directly by separating the system into distinct sub-systems with known Hamiltonians and then uses the Fermi golden rule to obtain the transition probability, assumed to be constant in energy. Stratton first applied it to tunneling between two conductors through an insulator, assuming parabolic energy-momentum relations [33], and later to SBs [24]. The main shortcoming of the latter paper was that the pre-exponential terms in the forward and reverse bias resulted in different constants, such that it was unable to obtain zero current at zero bias. This was resolved by the work of Crowell [13], who noticed that due to image charge lowering the barrier occurs not at the metal/semiconductor interface but inside the semiconductor. Therefore, the effective mass in the Richardson constant should always be that of the semiconductor.

Following Crowell, the tunneling current from the semiconductor to the metal (after integration over momentum transverse to the metal/semiconductor interface) is given by [34]

$$\begin{eqnarray}&&J=\displaystyle \frac{{A}^{* }T}{{k}_{{\rm{B}}}}{\int }_{0}^{\infty }d\xi \left[{f}_{{\rm{s}}}\left(\xi \right)-{f}_{{\rm{m}}}\left(\xi \right)\right]{ \mathcal T }\left(\xi \right),\end{eqnarray} \tag{ 6 }$$

where f_s(ξ) and f_m(ξ) are respectively the Fermi–Dirac distribution functions of occupied states on the semiconductor side of the junction and unoccupied states on the metal side of the junction, and ${ \mathcal T }(\xi )$ is the one-dimensional transmission probability for the barrier with an energy ξ, associated with the component of momentum normal to the metal-semiconductor interface. Note that this equation can also describe TE when ${ \mathcal T }(\xi )=1$ and the limits of integration extend to the top of the barrier. In this framework, calculating the tunneling current is reduced to calculating the transmission coefficient.

Before discussing how the transmission coefficient can be calculated, we first briefly discuss the Richardson constant A^*, which appears in both the tunneling and the TE equations. In the ideal theory A^* is defined by equation (5), but the effective mass used in this equation can be different for direct tunneling versus thermally assisted tunneling and TE [13, 25]. Nevertheless, this work assumes that the effective mass should be that of the semiconductor and independent of the metal and that there is no interfacial oxide layer between the metal and the semiconductor. Research by Toyama has shown, however, that the Richardson constant varies with film thickness [35, 36]. Work exploring tunneling of metal-insulator-semiconductor junctions showed that the effective mass of each region needed to be included in order to correctly match boundary conditions [37, 38]. Variations of the Richardson constant from the ideal value are thus often attributed to the presence of a tunnel barrier at the MSJ and the resulting impact due to the additional prefactor from this mismatch of effective mass. More recently, the effective mass of the metal was used to obtain a value intermediate between that of the metal and that of the semiconductor, and was used to explain TE transport in SB SiC diodes [39].

The transmission coefficient T(ξ) has been the target of many different approximations. The most extensively used technique is the Wentzel–Kramers–Brillouin (WKB) approximation, which assumes that the amplitude of the wavefunction varies slowly compared to the phase so that, as in the classical case, the total energy is greater than the potential energy [40–42]. The Gundlach method [43] assumes that the potential barrier is linear, and transforms the Schrödinger equation into Airy functions. The transfer matrix method approximates the barrier in the transport direction as piecewise linear functions and determines the transmission coefficient for each one. Finally, the wavelet methodology approximates the wavefunction by a wavelet [44, 45].

We briefly recall the WKB approximation for determining the transmission coefficient [40–42]:

$$\begin{eqnarray}&&T(\xi )=\exp \left(-\displaystyle \frac{2}{{\hslash }}{\int }_{{x}_{1}}^{{x}_{2}}\sqrt{2m(V(x)-\xi )}\ {dx}\right),\end{eqnarray} \tag{ 7 }$$

where x₁ and x₂ are the classical turning points, ξ ≤ V(x) and equation (7) is real. This approximation has been extensively explored by Padovani and Stratton [24] for barriers of arbitrary shape. Most often, however, it is approximated as triangular, with V(x) = q ϕ_Bn0 − qEx. This results in the analytical solution

$$\begin{eqnarray}&&T(\xi )=\exp \left(-4\displaystyle \frac{\sqrt{2{m}^{* }}}{3{\hslash }{qE}}{\left(q{\phi }_{\mathrm{Bn}0}-\xi \right)}^{3/2}\right),\end{eqnarray} \tag{ 8 }$$

which leads to Fowler-Nordheim type equations.

As devices are scaled down, three-dimensional calculations become inaccurate. Other formalisms that can be employed include Wigner functions, the non-equilibrium Green's functions (NEGF)—Landauer method and/or combining these with ab initio calculations. The Wigner distribution function method [46] has typically been used to explore transport in systems far from equilibrium, most notably resonant tunneling diodes [47], where the non-stationary description is important. It models the system using a density operator (the Wigner function) whose time evolution is given by the Liouville-von Neumann equation. Solutions can be obtained using either finite difference or Monte Carlo methods. This technique has also successfully been applied to explore quantum transport in ultra-scaled MOSFETs [48].

A large majority of the models that are used to model transport through the SBs in SBMOSFETs are based on the semi-classical TE and tunneling methods because the quantum methods consume large computing resources for just the calculation of transport at the SB. Quantum techniques that describe transport in SBMOSFETs typically use the SB height as a boundary condition, grouping the different types of transport into a unified treatment [49, 50].

During the past 25 years, research has shown that Si SBMOSFETs are intrinsically lower cost, more energy efficient and inherently more scalable than conventional doped source/drain MOSFETs [7–9]. As a result of the many obstacles in realizing this technology, however, there has been little industrial exploitation. We briefly review their fabrication and advantages as they serve as a basis for all the SB transistors considered in this review.

SBMOSFETs as depicted in figure 3(a), are realized by depositing a metallic layer onto the semiconductor source and drain contact regions, typically with a self-aligned process. To ensure reproducible, void-free and geometrically well-defined metal/silicon interface regions, a post-deposition anneal (PDA) step is carried out. In silicon the metallic region formed by the PDA typically results in a metallic alloy, known as a silicide [51]. These materials have been widely used in conventional doped source/drain FETs (DSDFETs) to realize ohmic contacts at the doped source and drain regions, as well as for doped poly-Si gate electrodes. The formation of many metal silicides is a result of the diffusion of the metallic atoms into the silicon. For SB transistors this leads to an overlap of the source/drain regions with the gate and additional control over the band bending near the interface. MSJs involving low-doped silicon result in Fermi-level pinning closer to the valence band edge, resulting in a low SB height for holes. Rare-earth silicides such as those involving yttrium, erbium, holmium, dysprosium and gadolinium [52] form low n-type Schottky barriers to silicon. By comparison, for Ge, where the metallic compounds are known as metal germanides [53], there is generally a lower phase stability compared to silicides.

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Depending on the SB height of the junctions, two distinct operating regimes are differentiated: (a) unipolar SBMOSFET with small barrier height or near-ohmic contacts for electrons or holes and (b) ambipolar SBMOSFET with a substantial barrier height for both electrons and holes. An ideal SBMOSFET for high performance computing corresponds to type (a), with the SB at the source playing a significant role in preventing the 'off' state leakage current between the source and the channel [7]. In the on state the SBs would become nearly or even completely transparent and the device would operate as a conventional doped source/drain FET (DSDFET). In the ideal case then, the difference in transport would be predominantly found in the sub-threshold region. For low power analog electronics, case (b), ambipolar SBMOSFETs can be employed, as will be discussed in the section on ubiquitous computing. Figure 4 shows a schematic band diagram and transfer characteristics of a Si SBMOSFET device. Figure 4(a) is biased as a p-type transistor in the on state, where the band bending is inverted so that not only TE over the barrier occurs but also direct and thermal assisted tunneling processes. These are the same processes described for MSJs in section 1.2. An example of the characteristics of a pSBMOSFET is shown in the device in figure 4(b) with a Subthreshold Swing SS of 92 mV Decade^–1. Understanding the current transport mechanisms in the sub-threshold and other regimes of operation is an important part of the literature. Note that the effective barrier to transport in the sub-threshold regime includes not only the SB height, but also the height of the bands that rises above it. In this region, transport occurs by TE and the current is very small. Nevertheless, the changing effective barrier height to carriers, due to changes in gate potential, causes large changes in the sub-threshold current in the channel. The threshold voltage in bulk SB devices can thus be defined as the V_g value corresponding to the flat-band voltage [54].

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Ideally, on-state device performance is equivalent to that of DSDFETs. In practice, however, this will occur only when the SB is completely transparent, which is challenging to achieve. Nevertheless, linear or ohmic contacts can be realised by strong or even degenerate doping of the semiconductor, where the SBH to the valence or conduction band edges can be reduced to 0.1 eV. Moreover, for doped Si and Ge semiconductors a special situation can occur during the PDA when the phenomenon of dopant segregation takes place. This has been observed experimentally through ion SIMS profiles and further described theoretically with DFT calculations by Kinoshita et al [57]. Typical dopant impurities for Si and Ge, like P, As, Sb and B, show a low or even zero solubility in many metal silicides and germanides [58]. Consequently, during the metal-silicide/-germanide growth, the impurity atoms initially residing in the transformed semiconductor region are dissolved and displaced by diffusion and finally accumulate in the semiconductor adjacent to the MSJ. Measurements show that the dopant atoms are not built into the semiconductor lattice because of the low silicide formation temperatures. Instead, they tend to reside as interstitials, influencing the band alignment at the Schottky junction. Experiments demonstrated that B and As dopants in CoSi₂/Si junctions [57] and B, P and As dopants in Ni_x Si_1−x /Si films [59] are the most efficient for dopant seggregation.

The SB at the source/drain will thus influence the flow of current and the distribution of charges and depend on the device materials, the voltages, temperature of operation and other factors such as interface states, barrier inhomogeneities [60], etc. The device physics of the SBMOSFET can be quite complex. We now address the more subtle differences between SBMOSFSETs and DSDFETs with a focus on the advantages of SBMOSFETs.

1.3.1. Charge transport near the Schottky barrier

The metallic source/drain electrodes constrain the electric field to be normal to their surfaces and will be determined almost exclusively by the shape of the metallic electrodes, as shown in the simulations in figure 5. This contrasts conventional DSDFETs, where, except in specific circumstances, such as near the drain under high drain voltage, the field near the source is largely vertical. It is independent of the details of the source/drain regions, as shown schematically in figure 3(c) and in the lateral direction by the simulations in figure 5. Carrier emission from the source is simply from one type of silicon to another and there is no abrupt change in velocity as charge carriers transit from source to channel.

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Multiple authors have explored experimentally and via two-dimensional (2D) technology computed aided design (TCAD) simulations the effects of a metallic source/drain on device performance. A review from 2006 describes earlier devices [7], while Valentin [61–63], Pearman [64, 65], Raskin [66] and Du [67] have documented the differences in transconductance (g_m), gate capacitance (C_gg) and unity current gain frequency (f_T) between SBMOSFETs and conventional DSDFETs. All of these investigations show that despite reductions in g_m, f_T is higher for SBMOSFETs compared to DSDFETs because of significant reductions in C_gg. The root cause of the reductions in C_gg with finite SB height at the source/drain junctions remains unclear, but we see two possibilities. The first is that the SB limits transport in the channel resulting in less charge and therefore less sensitivity in the channel region to changes in gate voltage, as explored by Valentin [61] and Pearman [64]. The second one is that strong lateral electric fields near the source result in 'hot' charge carriers—carriers not in thermal equilibrium with the lattice—transiting the channel at a depth somewhat beneath the gate oxide. These carriers are likely 'hot', due to large initial velocities when emitted from the metallic source electrode, where Fermi velocities can be 10–20 times the saturation velocity of carriers in silicon. A qualitative comparison of the inversion layers—not based on simulation but rather educated approximation—is shown in figure 6. Within the Thomas–Fermi approximation, carriers leaving the source will travel approximately the Debye length before their velocity adjusts to that of the semiconductor [5]. Such effects have been especially observed to result in a strong injection of charges from the source into the gate in asymmetric transistors with a single source SB, such as in [68]. This effect should become more important as device dimensiond approach the Debye length, (20 nm at a doping of 1 × 10¹⁷ cm⁻³[5]). Its existence could explain, at least in part, the observed decrease in C_gg.

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A series of papers by Shih, Luo and co-authors [69–73] have examined, both via 2D TCAD simulation and experiment, the effects of metallic source and drain electrodes on the performance of both floating gate and charge trapping non-volatile memory cells. Their results show how charge carriers near the source attain velocities large enough to enable charge trapping in oxide-nitride-oxide (ONO) structures, something that is not observed in conventional DSDFETs, in accordance with the schematic depiction in figure 6. Further, programming efficiencies are observed to be several orders of magnitude larger for SBMOSFETs, which can be explained by large velocities near the source. Simulations of injected charge in ONO films show the lateral extent of the charge distribution to be around 20 nm, about 3 × smaller than for conventional DSDFETs, and in agreement with the order of magnitude of the Debye length.

The effects of these source-side hot-carriers on long-term device degradation and reliability has received little attention in the literature and is a field of study that deserves significant attention.

1.3.2. Lower parasitics and off current

There are two parasitics that can be significantly different in SBMOSFET devices: the parasitic series resistance, the parasitic bipolar gain. The parasitic series resistance, defined as unwanted resistance external to the channel of the transistor, is greatly reduced in an SBMOSFET compared to a conventional DSDFET. The MSJ resistance, which is the largest component in a DSDFET, is now technically part of the channel in an SBMOSFET and is therefore no longer parasitic. While this may seem a mere exercise in semantics, there are important differences. In DSDFETs, the resistance associated with the SB, R_SB is generally a fixed, constant number and depends only on the SB height and doping density on the semiconductor side. Often, a mid-gap SB system is used (for both p and n-FETs), with a high doping density.

As we saw from our discussion above, R_SB for an SBMOSFET strongly depends on the gate voltage. Typically a metal with a low SB to the conduction band of the semiconductor is used for n-type devices and a metal with a low SB to the valence band is used for p-type devices, with the exception of RFETs, which require mid-gap SB heights. The overall channel resistance of an SBMOSFET, including the Schottky junctions on either end, is therefore a strong function of the gate voltage. The sheet resistance of the metal, R_sh, which is 1–2 orders of magnitude smaller than that of doped silicon, is still present, depicted in figure 7. There is also the very small metal-to-metal contact resistance (R_con) to the plugs, which connect to upper metal layers. The parasitic resistance in an SBMOSFET is therefore an almost negligible fraction of the total resistance (typically ∼1% or less [7]). For a conventional DSDFET the parasitic resistance can be much larger, as high as 50% in highly scaled devices.

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An n-type DSDFET typically has heavily doped n-type source/drain regions and an oppositely doped (p-type) body region. As a result, there is an unavoidable parasitic NPN bipolar transistor. Under normal operating conditions this NPN is dormant, as the base-emitter junction is not forward biased because the source and body potentials are usually tied together or, in some cases, reverse biased. However, the body can become forward biased with respect to the source if, for example, the p-type body is filled with holes resulting from either impact ionization in the inversion layer or from an ion-strike. The NPN can then become activated and will amplify the original hole current into a much larger electron current. Bipolar amplification gains of around ∼200 × are typical for silicon NPN devices. Worse, this mechanism can, under the right conditions, become self-sustaining and uncontrolled by the gate electrode, usually resulting in the destruction of the device and the surrounding circuitry. This positive feedback loop can occur within single transistors or in CMOS circuits with complementary n- and p-type devices. Modern device designs such as fully depleted silicon on insulator, FDSOI, Tri-Gate FETs, FinFETs, and GAAFETs attempt to mitigate this problem by operating at low supply voltages to minimize impact ionization and also by minimizing the volume of the body region to limit charge collection during an ion-strike. SBMOSFETs, however, have a key advantage in this respect: the gain of the NPN device is much less than unity, and therefore the positive feedback loop mentioned previously cannot exist. This is due to differences between the physics of current transport across a Schottky junction (thermal emission) vs a p–n junction (drift-diffusion). As a result, SBMOSFETs are inherently immune to all parasitic bipolar action. This is true regardless of device profile, doping profiles, ionization radiation intensity, temperature, device layout, operating voltage, etc. Device design is thus liberated from having to consider unwanted bipolar gain, providing a real advantage especially in some cases, for example in power devices.

Minimizing the off-state leakage between source and drain in DSDFETs is a major challenge for highly scaled devices where direct source-to-drain tunneling currents can occur. The presence of a finite SB at the source/channel interface therefore provides SBMOSFETs with a built-in advantage. Modern device designs such as the tri-gate FET, FinFETs and gate-all-around FETs (GAAFETs) are all attempts to exert greater gate control over the channel in order to reduce off-state leakage while keeping on-state drive current large.

The leakage currents in a conventional DSDFET are controlled by creating electrostatic barriers in the channel, denoted as ϕ_es, by introducing dopants of the appropriate type, concentration and location into the substrate, and/or gate material engineering. These techniques work equally well in an SBMOSFET and serve to augment the existing SB, ϕ_SB, in order to create a larger total barrier (ϕ_tot) and lower the leakage current. The presence of a finite ϕ_SB allows for a measure of flexibility in device design. Specifically, ϕ_es can be reduced via channel doping and/or gate material engineering, to keep the leakage current constant compared to the zero-ϕ_SB case. Simulations have shown that the channel doping for a 25 nm SBMOSFET can be reduced by as much as 1–2 orders of magnitude [7]. Reductions in channel doping may also lead to beneficial reductions in gate and junction capacitance, due to the wider extension of depletion regions. Of course, the presence of a SB will also impede the flow of current in the on state. The net effects of the SB on both the drive and leakage currents will depend on the details of the device architecture: SB height, source and drain position and profile, channel dopants, channel length, etc.

As devices approach the sub-10 nm regime, direct source-to-drain tunneling becomes important in MOSFETs. Simulations by Cho et al used NEGF simulations to compare sub-10 nm SB and double-gate MOSFETs and showed that methods such as source/drain underlap and optimization of the body thickness can suppress direct source-to-drain tunneling in both devices, but that the double-gate MOSFETs show higher performance due to higher drive currents [8]. The caveat of this work, however, is that the SB was assumed to be 0.1 eV, and image charge lowering was not considered. Semiclassical simulations that do take this into account suggest that at nanoscale sizes the image charge lowering can reduce the barrier sufficiently to make it transparent [9].

1.3.3. Improved Manufacturability

If the metallic source/drain regions of an SBMOSFET are silicides, as is almost always the case in Si devices, there are several manufacturability advantages compared to a conventional DSDFET (figure 8). Most important are the simplicity and lower energy associated with the silicide formation. Metal deposition, anneal and unreacted-metal strip are done at much lower processing temperatures compared to doping, and are high-throughput and high-yield steps. Silicides for both p and n-type devices, for example PtSi and ErSi₂ respectively, are typically formed at 450 °C, cause no damage to the lattice, and result in low-resistance films that have atomically abrupt interfaces to the silicon substrate. The final lateral and vertical extent of the silicide film is determined by the thickness of the original metal layer, which, once reacted to completion, is invariant with additional annealing, thus providing a wide process margin. The contact resistance of these silicides to metal 'plugs' from upper metal layers is also very small, as expected for metal-to-metal contacts. Overall the SBMOSFET will have fewer processing steps and also consume less energy due to removal of the doping steps. Therefore, it remains a very interesting device for industrial use, especially for applications seeking to reduce energy consumption and process complexity.

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2D materials are an ultimate solution to thinning the transistor body to improve electrostatics. The atomic thickness may enable very small gate length 2D FETs, thus paving the way for gate length scaling into the nanometer and even sub-nanometer regime [76, 81]. The significant ongoing research and development effort has resulted in the technology being identified by the international roadmap for devices and systems (IRDS) as a potential candidate for devices beyond CMOS [2]. Nevertheless, a large contact resistance is observed in 2D devices, typically preventing experimental realizations that are competitive with contemporary Si or even Carbon NanoTube CNT technology.

These materials exist in a large variety of classes including metallic, semiconducting, insulating, and recently even magnetic and superconducting. The schematic comparison of 2D and bulk materials in figure 9 [81] shows how the surfaces of 2D materials are free from dangling bonds, consistent with physical properties at the monolayer regime [82–84]. A dominant critical issue is therefore the interface engineering and especially the optimization of the contacts. Several proposed solutions include inserting a buffer layer between semiconductor and metal, realizing van der Waals (VdW) contacts, edge contacts, novel doping and surface engineering. These techniques have been described in an excellent recent review [20]. Nevertheless, SBs can easily dominate the transport and many 2D semiconducting transistors are essentially small-scale SBFETs [85].

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Although the first exfoliated 2D semiconductor was reported in 1986 [86], it was the demonstration of the electric field-effect in single layer graphene, exhibiting unprecedented carrier mobilities and ballistic transport at room temperature [87], that sparked the recent intensive research effort. Graphene, however, has a zero band gap and is not suitable for logic applications, although it may find use in radio frequency applications [88]. Numerous 2D materials have been explored in this context for the past 10 years and are the subject of ongoing research to develop potential electronic applications [89, 90]. Of particular importance are single-layer 2D FET devices based on the transition metal dichalcogenide (TMDs) family, which have a general formula MX₂, where M is a transition metal (e.g. Mo, W) and X is a chalcogen atom (eg. S, Se, Te) [91]. Mo and W-based TMDs are semiconducting with a thickness-dependent band gap that transitions from indirect (bulk) to direct (up to a few-monolayers) [92]. Cao et al rigorously analyzed the performance and scalability of 2D semiconductors, especially MoS₂, through dissipative quantum transport simulations for sub-10 nm technology nodes [81]. Figure 10 clearly demonstrates that MoS₂ transistors outperform Si devices in terms of (a) evaluated SS and (b) drain induced barrier lowering (DIBL). In (c), calculated I_on for devices with different numbers of layers of MoS₂ and Si are compared for high performance and low standby power technologies. It is observed that MoS₂ devices show higher I_on compared to Si devices because of the poor electrostatics in the latter. More than 3 layers of MoS₂ must be avoided for sub-10 nm nodes, however, because of worsening electrostatics. Experimental MoS₂ FETs have indeed shown superior immunity to short-channel effects [93], and also high saturation velocity (2.8× 10⁶ cm s⁻¹) in few-layer devices [94]. Nevertheless, the main problem remains the high source/drain contact resistance. Shen et al have recently reported breakthrough results of ultra-low contact resistance using Bi contacts to MoS₂ transistors, and proposed that Bi-TMD technology could potentially meet the IRDS targets for logic transistors [95]. Nevertheless the thermal stability of this solution may prevent its large scale implementation.

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It has been more difficult to realize p-type TMD FETs due to strong Fermi-level pinning at the semiconductor interface with most metals, which also results in large contact resistances [96]. Li et al fabricated p-FETs based on few-layer black phosphorus (BP) that demonstrated reliable performance and ambipolar behavior [97]. Realization of transistors in ambipolar materials such as WSe₂ and WS [98] have also been explored. To date their device performance for high performance computing has not been assessed as well as the MoS₂ devices.

In order to improve the performance of existing FET technology based on 2D materials, different device architectures are also being investigated. These include devices based on vertical and lateral heterostructures of 2D materials. 2D–2D heterostructures are known to form either Schottky contacts or PN junctions, depending on the type of material used. Graphene is generally used as the contact material, while semiconducting 2D materials are used as the channel or junction materials, and hBN is used as the gate dielectric [99]. Heterojuction FETs based on heterostructures of 2D/3D materials are also being investigated. Here, 2D materials have an edge over conventional channel materials such as Si for the fabrication of ultimately scaled heterojunction FETs, as field-effect modulation of the current transport through the heterojunction provides a unique opportunity to realize band-to-band tunneling devices.

Perhaps the greatest promise for 2D materials for high performance computing is the possibility to design novel devices, and ultimately architectures based on stacking, that is not possible in conventional silicon technologies. Two recent review articles have detailed this in greater depth [100, 101]. In this way, the disadvantage of the source/drain contact resistance is offet by an advantage not possible in conventional semiconductor technologies.

Single-walled carbon nanotubes (SWNTs) and nanowires have been considered as potential building blocks for future microelectronic devices because of their very small diameters and the excellent properties exhibited by single-transistor devices. Like 2D materials, the connection between nanotube and metallic contacts results in a SB, but solutions are now available to render the barrier negligible in the on-state. Simulations predict impressive 5-fold [102] to 9-fold [103] improvements in the energy-delay product (EDP) (notably coming from lower-bias operation) in comparison to Si or Si/SiGe FinFETs. The two main difficulties have been synthesizing only semiconducting SWNTs and doping the nanotubes, but some laboratories have now met the criteria for ultra large scale integration [77]. In order to do justice to this very large body of work, we first provide an overview of the advantages and disadvantages of this technology. We then focus on the role of the SB between the nanotube and the metallic contacts.

SWNTs are hollow cylinders made of sp2-bonded carbon atoms, with a diameter in the 0.7–3 nm range. Their structure, properties and applications have been thoroughly reviewed [104–106], as well as their specific electronic and transport properties [107, 108]. Depending on their chirality (diameter and helicity), they can have a metallic or semiconducting character. In the latter case, their direct band gap scales as ∼0.8/d (with d the diameter in nm) so that typical diameters (1–1.4 nm) yield sizable band gaps (0.6–0.8 eV).

The most important assets of SWNTs in the context of carbon nanotube FETs (CNTFETs) are: (i) their atomic structure is free of dangling bounds and rugosity (which notably makes them compatible with high-κ gate dielectrics without mobility degradation [109–111]); (ii) their band structure is symmetric for holes and electrons (resulting in similar m^⋆ for both types of charge carriers); (iii) their capacitance is low [112], which is particularly advantageous at high-frequency [113, 114]; (iv) they have exceptionally high carrier mobility for both electrons and holes; (v) they can withstand extremely high current densities (>0.5 mA μm^–2 for arrays) [2]; and (vi) charge back-scattering processes associated to defects are not efficient; (vii) at low electric field the electron (and hole) mean free path associated with acoustic phonons is as high as 300–500nm. It is reduced to ∼20 nm at high electric field due to optical phonons [108, 115, 116].

Transport in SWNTs is mostly ballistic at low bias in long-channel devices (<300 nm) and at all biases in aggressively scaled devices (<20 nm). The mobility in long SWNTs (corresponding to low electric field) scales as d²/T [117], and at RT it has been estimated to be >10⁵ cm² V⁻¹ s⁻¹ for large diameter nanotubes [115]. The highest experimentally measured value, however, is μ = 79 000 cm² V⁻¹ s⁻¹ for an ultra-long SWNT (L > 300 μm) [118] but values in the 2500–20 000 cm² V⁻¹ s⁻¹ range are more typical.

This technology also has some disadvantages. The main one is the difficulty in synthesizing uniquely semiconducting nanotubes. In addition, substitutional doping, which is one of the great strengths of silicon technologies, is not possible in carbon nanotubes. Alternative chemical and electrostatic doping strategies exist but are often unstable (such as potassium or molecular doping) and/or poorly scalable (such as multiple gates). It also remains extremely difficult to control the selective placement of SWNTs. To obtain high enough drive currents, optimized CNTFETs need to be composed of several parallel nanotubes with an optimized CNT–CNT pitch (5 nm) [75, 102], small enough to allow high current densities but not too small to ensure that the advantage of 1D electrostatics can be maintained. Research therefore focuses either on demonstrating devices and circuits using FETs made up of arrays of CNTs, or transistors with an individual nanotube, to explore device properties and scaling. Arrays typically exhibit a degraded SS and leakage current [119], due to the presence of metallic nanotubes.

Individual SWNTs were integrated as channels in FETs as early as 1998 [120, 121]. In these devices and in most of the following ones, metallic source and drain electrodes directly connect the undoped nanotube channel so that they operate as Schottky-barrier FETs [122]. Such SBMOSFET operation is notably central to understand their (lateral and vertical) scaling behavior [109, 123–125]. The change in band gap with diameter renders large diameters subject to ambipolar leakage currents, and very small diameters susceptible to large contact resistance. The ideal diameter has been predicted to be ∼1.7 nm [102]. It is important to note that n- and p-type CNFETs operating as conventional MOSFETs (i.e. not as SBMOSFETs) were also fabricated by doping sections of the nanotube close to the metal source and drain electrodes. This resulted in improved performance but, as mentioned, the unstable chemical doping or poorly scalable multi-gate designs used strongly limit their applications when compared with simpler, more scalable self-aligned gate SBMOSFET designs [126]. Recent work has demonstrated a new electrostatic doping strategy to realize excellent control over the p-type and n-type CNTFETs using non-stoichiometric oxides [127].

A crucial difference between conventional metal/semiconductor Schottky contacts and nanotube/metal interfaces is the limited effect of Fermi-level pinning in the latter case. As a result, the SB heights in both p- and n-type nanotube SBMOSFETs were shown to principally depend on the metal work function and on the nanotube diameter (through its impact on the band gap), as shown in figure 11. High work-function metals (e.g. Au, Pd [128]) typically result in good p-type FETs, while low work-function metals (Sc [129], Y [130]) allow good n-type FETs. Interestingly, mid-gap alignment (i.e. high SB height for both electrons and holes) results in low drive currents for bulk-silicon SBMOSFETs, but on the contrary, leads to efficient ambipolar SBMOSFETs with carbon nanotubes [131]. Indeed in SWNTs, band bending occurs at the nm scale and the low m^⋆ favors tunneling through high (yet thin) barriers. Note that ambipolar nanotube SBMOSFETs were shown to be important in carbon nanotube optoelectronics, as reviewed in [132, 133].

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Another important observation is the significantly different device performance obtained with metals of rather similar work function. In particular, palladium was shown to be the ideal metal for p-type CNTFET, which cannot be accounted for by its work function alone. This led to a vast number of computational studies addressing the details of the metal/nanotube interface and the impact of weak versus strong interactions on the contact resistance (see notably [135] and references therein). In particular, the contact length L_c (the length of the nanotube section embedded below the source and drain metal contacts), which was initially mostly neglected became a central element in determining the ultimate performance of aggressively scaled devices [136, 137]. Weakly interacting metals (such as palladium) usually give the best performance when L_c is kept long enough (typically above 50–100 nm). But for short contacts, the contact resistance R_c scales as ${L}_{{\rm{c}}}^{-1}$ for most metals (Au, Pt, Pd).

Aggressively scaling the channel length only makes sense if L_c is also drastically reduced, which is why the details of the R_c(L_c) scaling are a central issue in the field. Figure 12 from [135] and [138] summarizes simulations and experiments, and highlights a key element going forward: metals with the lowest R_c at long L_c (notably Pd) may not be those with the best scaling trends. Conversely, Rh, which is not particularly remarkable for L_c = 100 nm, becomes a promising choice for L_c = 20 nm [138]. The current state of the art in terms of scaled contact length consists of either: (i) end-bonded molybdenum carbide contacts that allow high performance (2R_c < 36 kΩ/nanotube) down to L_c = 9 nm. Contrary to Pd and Rh contacts, the nanotube section below the annealed molybdenum metal is destroyed and replaced by a Mo₂C carbide, or (ii) more conventional Pd contacts with L_c = 10 nm, which do not require a high temperature annealing step but also yield 2 · R_c = 36 kΩ/nanotube as median value (and even 2 · R_c = 13 kΩ/nanotube for the best device) [139].

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Contact type and contact length optimization is clearly a key aspect for CNT-SBMOSFET improvement. However, the channel length scaling and the choice of the device topology (in particular of the gate stack) are equally important issues. Channel length scaling studies started as early as 2004 with L_ch lower than 50 nm [126] and it was later shown that CNT SBMOSFETs with L_ch = 15 nm do not suffer from short-channel effects. High performance CNTFETs with channel length below 10 nm [140, 141], even down to 5 nm, were then achieved [142]. In terms of geometry, a large majority of the experimental studies used planar back-gate or top-gate designs. Due to the cylindrical nature of SWNTs, it was naturally considered that a gate-all-around geometry would be ideal from an electrostatic point of view and this geometry was routinely used in calculations [124, 125, 143] In addition, its high symmetry makes the simulation less demanding. Such gate-all-around designs were successfully realized experimentally [144–146]. The cylindrical geometry efficiently shields the channel from parasitic charges, although it is not clear yet whether it actually leads to the best performance. Not only is it much more difficult to engineer, but recent studies have also shown that higher clock frequencies can be obtained with simpler geometries, as exemplified in figure 13 [147, 148], due to reduced parasitics.

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Although the material characteristics of carbon nanotubes were recognized as promising when they were discovered in 1991 [150], it took 20 years before their use was demonstrated in significantly complex circuits [151]. The research described in this section focused on aligned transistors, the channel of which is either an individual CNT or a large number of parallel CNTs with a channel length much shorter than the CNT length. Another class of nanotube-based devices are CNT-TFTs, for which the channel is a dense array of randomly oriented CNTs with a channel length either longer or shorter than the average CNT length. CNT-TFTS were initially considered for applications that required low to moderate performances (in particular for flexible electronics or flexible displays), because either the density of CNTs was not high or because the channel dimensions were micron size, resulting in relatively small mobilities. These types of CNT TFTs are briefly discussed in section 3.4. More recent research has shown how non-aligned arrays of CNT transistors can be used to realize high speed logic (2 GHz) using high-purity solution processing [152] and how high-performance devices are compatible with fabrication in commercial silicon manufacturing facilities [153]. In the latter reference, simulations showed that the impact of non-aligned TFTs, as compared to aligned arrays, is less than 20% when channel lengths are smaller than 500 nm, and the density of tubes is below 56 tubes/micron. We thus see that many of the problems in realizing CNT devices, such as the purity and positioning, have solutions, and we can expect to see demonstrations of high-performing complex circuits of CNTs in the coming years [154], with the potential to move CMOS beyond Si [149, 155].

Compared to the CNTs described in the last section, semiconductor nanowires are not closed, allowing the possibility to form bonds with a surrounding medium, for instance with a dielectric material. By varying the nanowire diameter, the electronic structure can be tuned from that of the bulk to one exhibiting quantum confinement, occuring when the diameter is comparable to or smaller than the Fermi wavelength of the semiconductor material. In addition to the possibility of exploiting the one-dimensional density of states, nanowires allow for monolithically combining different materials, which is the relevant for MSJs, both in longitudinal and radial coordinates. Here we focus only on how this type of transistor can be used for SBMOSFET devices.

Semiconductor nanowires are highly promising for implementing diverse types of emerging electronic and optoelectronic devices making efficient use of Schottky junctions. Distinctly different from bulk and thin films, this one-dimensional structure allows for an enhanced relaxation of mechanical lattice strain when combining materials with highly mismatching lattice constants and crystal structures [156]. Metal-nanowire SBs can exhibit unique properties related to the diameter [17, 22, 157, 158]. SBMOSFETs built from nanowires can achieve the ultimate electrostatic gate coupling to the channel and SB when a surround gate stack (thin insulator oxide with high dielectric constant and metallic gate electrode) is employed and the semiconductor body is sufficiently thin. A practical method to assess the influence of the channel potential to an externally applied electric gate field and thus the scalability of MOSFETs and SBMOSFETs is given by the so called natural length of the transistor. The method, has been applied to different MOSFETs in analogy to a Debye screening length, considering a specific channel geometry, doping concentration, gate insulator and gate electrode architecture. The natural length describes a critical distance, typically measured from source, across the channel length upon which the potential and thus the bands react to the external field, and is thus often taken as a figure of merit to compare the scaling behavior between different MOSFET architectures. Through this approach Auth and Plummer described the scaling behavior of surround gated semiconductor nanowires [159], proving its efficacy in reducing short channel effects.

Nanowires have been fabricated both by conventional top-down fabrication schemes, i.e. using deterministic lithographic definition and etching or depositing material, as well as by bottom-up growth techniques. In the latter self-assembly features take place, avoiding the need to define geometries via a lithographic mask [80, 156]. Bottom-up approaches like the catalyst particle assisted vapor liquid solid growth mechanism, or the growth in porous filaments in alumina templates, may lead to smooth surfaces and ultra-small diameters, but usually show limitations in deterministic position control. Finally, nanowire conducting channels can also be formed electrostatically in thin films by multi-gated electrostatic confinement [160].

For Si and Ge nanowires, SBMOSFETs can be built either by covering the nanowires with metallic top electrodes, or by intruding a metal silicide within the nanowire, thus creating a longitudinal nanowire heterostructure [161, 162]. Although the first method typically provides a larger metal-semiconductor junction area (surface contact), the transistor performance is generally degraded as the junction region is shielded from the gate field. In contrast, intruded metal nanowire heterostructures introduce the Schottky junction within the nanowire [156], spanning a nanometer-scale junction area across the nanowire cross-section. This mostly ensures comparable junction areas in the same nanowire. In contrast to thin films and bulk, the nanowire system allows for the creation of the ultimate flat junction with atomic-level precision [163, 164]. Furthermore, the needle-like metallic nanowire segment and exposition of the Schottky junction provides an efficient coupling to external electric fields from the source-drain and gate biases [162].

In addition to compound metallic materials such as metallic silicides and germanides, elemental metal electrodes can be intruded into group-IV semiconductors, creating an atomically sharp and flat junction by an exchange reaction. Therein, the in-diffused metal species replaces the host semiconductor material entirely due to the low solid-state solubility gap, and is driven by a high asymmetry in diffusion coefficients. This was first reported by Lugstein et al for the Al–Ge nanowire system [165], and has recently been found to be likewise applicable to the Al–Si nanowire system [166], as well as for Al/Si_x Ge_(1−x) nanosheets involving the formation of a small Si interlayer [167].

The behavior of nanowire-based SBMOSFETs follows the description of the two cases described in section 1.3, (a) near-ohmic contacts and dopant segregated contacts and (b) SB contacts. Dopant-segregated contacts have been achieved in Si nanowires via the thermally driven intrusion of Ni_x Si_1−x into Si nanowires [168–170]. Due to this dopant segregation method, several emerging transistor concepts have been implemented, such as accumulation-type FETs similar to junctionless FETs [170], as well as devices with implanted source/drain regions and dopant-segregated sharp junctions, realizing a band-to-band tunnel FET with steep SS with a silicon nanowire material [171, 172]. The mid-gap SB devices are revisited in the next section because their smaller on currents precludes their use in high performance devices.

Figure 15 illustrates the concept of a SGT [11, 197, 198], where a barrier at the source is used to specifically control the drain current. As a result, SGTs have a large intrinsic gain, which is independent of both voltage and geometry. This concept allows low saturation voltage, low power operation and increased stability and uniformity. The disadvantage is the lower speed due to the extra capacitance at the gate/source, and lower drive current due to the saturation at the source barrier before pinch-off in the channel. Device scaling is determined only by the channel width (W), because the source contact is shielded from the drain [11, 199, 200], and not the ratio of channel width-to-length, as in conventional transistors. SGTs therefore exhibit reduced short channel effects compared to TFTs that function in the conventional way. Performance independent of the channel length has been demonstrated down to 360 nm [174]. SGTs are especially promising for low cost manufacturing technologies because they can overcome the intrinsic processing variability of such techniques.

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Several non-crystalline materials have been used as active layers in SGTs [201]: a-Si:H [11, 202, 203], polysilicon [199, 204] and semiconductor oxides, in particular ZnO [200, 205]. If an additional independent gate to the channel is added to control carrier transport, known as the multimodal transistor, further functionality can be obtained [206]. Recent work shows how the key to achieving high performing SGTs lies in the optimization of the relative oxide to source capacitance [207].

We first briefly highlight some results on SGT transistors in a-Si:H TFTs, which have achieved high-performance with good frequency response and excellent stability [11]. Typical devices are fabricated by using a chromium gate metal electrode and source/drain contacts on glass substrates, a silicon nitride gate dielectric and a-Si:H deposited by plasma-enhanced chemical vapor deposition at 250°C. A phosphorus implantation is used to control the effective SB height at the source/drain. Device characteristics exhibit very stable drain currents with less than 2% variation when applying constant gate and drain voltages at 30 °C for 24 h. Numerical simulations show that this behavior is due to a decrease of the SGT carrier concentration at the source end because of the formation of a depletion region. The higher electric field near the source also contributes to a reduction in the transit time and a corresponding increase in the cutoff frequency (up to 1 MHz). Higher values of the cutoff frequency can be achieved by decreasing the dielectric and the a-Si:H layer thicknesses. Sporea et al [197] reported that the use of a self-aligned polysilicon-based SGT architecture could result in an intrinsic gain of 1000. The device used a dielectric layer consisting of 200 nm SiN_x and 200 nm SiO₂, and an a-Si:H 40 nm layer, which was baked at 450 °C to obtain polysilicon. A high p-implant concentration was used to form the drain-contact regions aligned with the gate. Most notably, this architecture suppressed the kink effect and leads to a very large output resistance.

An organic TFT (OTFT) uses a thin film of organic semiconductor as the channel material. The basic OTFT has a structure similar to an SBMOFET, with a metallic source/drain contacting the organic channel. The substantially fewer carriers in organic semiconductors and the polycrystalline nature of many OTFTs result in short-channel effects at much larger sizes and feature lengths. For long-channel transistors, at several tens of microns, the R_SB is parasitic to device function and has only a minor impact on the device characteristics. To function in the RF regime, however, a large reduction of the OTFT channel lengths is necessary, and the contact resistance becomes crucial [208]. In addition to this role in more conventional operation, organic devices have also been used to realize source-gated transistors. In this section we discuss both of these applications.

The first OTFT was demonstrated in 1986 by Tsumura et al [209]. The main challenge for commercially viable devices is the low mobility of the transistors. Organic TFTs can be realized in conjugated polymers and conjugated small-molecule materials, the latter having in general better mobility [210]. Single crystalline films exhibit the largest mobilities, up to 40 cm² V⁻¹ s⁻¹ [211] for pentacene, but are harder to fabricate for large-area applications. A breakthrough in 2012 by Li et al demonstrated record mobilities up to 10 cm² V⁻¹ s⁻¹ [212] using a method that produces large-area single-crystalline organic thin films. The most promising applications take advantage of the natural mechanical flexibility of organics to integrate different types of substrates using fabrication with relatively simple and low temperature processing (<200 °C). OTFTs are therefore highly compatible with flexible substrates based on polymers and even paper.

A schematic view of the OTFT realized in coplanar and staggered architectures is shown in figure 16. Note that in comparison with figure 14, in addition to an aluminum oxide layer, the dielectric also includes a single molecular layer, known as a self-assembled monolayer, that can be used advantageously tune the properties of the device. A voltage applied to the gate induces an accumulation layer at the insulator-semiconductor interface, forming a conducting layer of holes or electrons, depending on the polarity of the gate bias. The polarity of the device depends on the type of carriers that can be injected from the electrodes into the channel region. If the Fermi level of the metal is close to the highest occupied molecular orbital (HOMO) of the organic material, then the injection of holes is enabled for a p-type device, as illustrated in figure 17. In contrast, if the Fermi level of the source is close to the lowest unoccupied molecular orbital (LUMO), an injection of electrons is possible, and the device is n-type if electron transport is possible.

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In the ideal case, a matching of the HOMO in p-type devices (or LUMO for n-type) to the Fermi level of the metallic electrode would result in an ohmic contact with high conductivity and the accumulation channel alone controls the device current. In practice, the work function of the metal does not perfectly match, and a SB results bias-dependent resistance that is controlled by the gate electrode, as in an SBMOSFET. The substantially fewer carriers in organic semiconductors and the polycrystalline nature of many OTFTs result in short-channel effects at much larger sizes and feature lengths. Device operation is therefore typically restricted to several tens of microns. For long-channel transistors the R_SB is parasitic to device function and has only a minor impact on the device characteristics.

To function in the RF regime, a large reduction of the OTFT channel lengths is necessary, and therefore minimizing the contact resistance is crucial [208]. At reduced channel lengths of order ∼μm, the injection of carriers at the source SB begins to have an important impact and cannot be neglected [213–217]. It results in a nonlinear S shape in the output characteristics, as illustrated in figure 18. Here, measurements on TFTs with a DNTT (dinaphtho[2,3-b:2ʹ,3ʹ-f]thieno[3,2-b]thiophene) organic semiconductor in a staggered architecture (bottom gate, top contact) are shown for a device with a channel length of 1 μm. Fitting a physics-based compact model from [213] to the measurement data results in an effective SB height at the source of Φ_B0 ≈ 0.35 eV, which in the model is in series with an ohmic contact resistance of R_c W_ch ≈ 117 Ωcm.

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There have been several successful attempts to reduce the contact resistance and improve overall device performance. Contact doping reduces the contact resistance, possibly by reducing the width of the SB at the interface and/or by filling trap states in the organic semiconductor regions close to the contacts [218]. Another technique is to use SAMs at the interface between the contacts and the semiconductor in order to optimize the morphology of the organic material close to the contact and hence lower the SB height. A PFBT (pentafluorobenzenethiol) treatment of gold bottom contacts has successfully been applied before the deposition of the organic semiconductor for improving the charge injection across the SB [219]. This technique has allowed transit frequencies up to 21 MHz using 0.6 μm channel length transistors [208].

In summary, OTFTs have an SBFET architecture. The limitations of the SBs can be minimized by several technological approaches, which allow the accumulation channel to dominate the transport characteristics. However, if the channel length is reduced to the sub-micrometer regime, the impact of the SBs become non-negligible. One possible solution to realizing very small organic transistors is to use SGT operation [220], as discussed in section 3.1. In this case the channel does not limit the transport and the appropriate design of the transistor has shown to allow excellent characteristics down to sub 400 nm [174]. Nevertheless, SGTs will in general not be able to attain speeds as high as devices operated in conventional TFT modes due to the large gate-source depletion capacitance.

Oxide semiconductor TFTs are promising devices for large-area electronics due to their compatibility with flexible substrates, low-temperature processing, higher electron mobility compared with OTFTs, and high stability. An 32-bit ARM processor has already been demonstrated in this technology [221]. The main disadvantage of oxide TFTs is that p-type TFTs have much lower mobilities and although realization with p-type organic semiconductors have been demonstrated, to date the technologies are too different to make integration in foundries viable. Like organic semiconductors, the transistors ressemble SBMOSFETs with a metallic source/drain contact, but in their regime of operation the SB is rendered unimportant. Like organic TFTs, they have been considered as SGTs.

Metal-oxide TFTs were first demonstrated with SnO₂ [222]. Investigations in this area gained traction after the discovery of colossal magneto-resistance in La–Ca–Mn–O thin films [223] and the subsequent increased interest in oxide films deposited using techniques such as pulsed laser deposition. The demonstration of a transparent ferroelectric TFT on a SrTiO₃ substrate [224] is particularly noteworthy. In addition, the increasing importance of transparent electrodes for flat-panel displays, solar cells and organic light-emitting diodes, also led to research on improving the materials for the semiconducting channel in TFTs [225]. A breakthrough occurred in 2003 with the demonstration of single-crystalline indium gallium zinc oxide (IGZO) n-type TFTs with high mobilities (80 cm² V⁻¹ s⁻¹) [226], and the subsequent demonstration of TFTs on a flexible foil [227].

Amorphous IGZO TFTs are now able to realize mobilities higher than 10 cm² V⁻¹ s⁻¹, I_on/I_off ratios higher than 10⁷ and SSs close to the ideal value [228–233]. Figure 19 depicts the geometry of a recently demonstrated device. The performance of n-type amorphous (a)-IGZO transistors have been used for high-end active matrix LED displays. Their performance depends on whether the material is vacuum deposited (average mobilities >20 cm² V⁻¹ s⁻¹) [234] or solution-based n-type metal-oxide TFTs (average mobilities ≈10 cm² V⁻¹ s⁻¹) [235]. Because p-type oxide TFTs have generally shown much lower mobilities, although up to 5 cm² V⁻¹ s⁻¹ have now been demonstrated [235], organic TFTs may provide a complementary solution for realizing more complex computing devices [236]. Source-drain ohmic contacts are, of course, the most often pursued on IGZO, and their quality depends on the contact material [234, 237]. In most cases, the electrodes are metallic, although indium tin oxide (ITO) has also been used, in particular for transparent devices [238]. An excellent overview of this technology is given in [178].

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SGTs have also been considered in oxide transistors [239]. ZnO SGTs were a natural choice because of its high electron mobility, wide band gap, good stability, easy low-temperature synthesis, and high breakdown fields [240]. As in other SB devices, below a certain gate voltage, a transition from TE to tunneling occurs [241] (figure 20). As in unipolar SBMOSFETs, this transition voltage can be identified with the threshold voltage in ZnO SGTs, since at that bias value the SB is thin enough for carriers to easily tunnel though it, therefore significantly increasing the drain current and turning the device on.

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SB IGZO TFT fabrication is more challenging than ZnO SGTs, because of the difficulty in achieving both the high channel conductivity and the low SB heights required for its operation. In [242] an SB IGZO TFT was demonstrated. To create a Schottky contact at the source/drain contact of the IGZO TFT, the electron concentration in the IGZO film was reduced by means of a high oxygen-gas partial pressure (against argon-gas), during an RF sputtering process (figure 21). Thermal annealing was carried out to achieve a more reliable contact. The properties of the SB were exploited in deep subthreshold and low-voltage operation, with an intrinsic gain as high as 400, which is very promising for analog signal-processing applications. In this work, the effective barrier lowering at the source is responsible for a decrease in the SB width and an increase in tunneling current. It accounts for the higher transconductance in the SGT versus the conventional IGZO devices. Further studies of IGZO SB contacts found that the reverse current is drastically dependent on the IGZO thickness, which seems to be related to the inhomogeneous nature of the SB height. IGZO SGTs with extremely high intrinsic gain were reported in [174]. In that work, 10–100 nm thick IGZO films were grown on SiO₂-Si wafers with 100 nm thick SiO₂. RF sputtering was also applied for Pt deposition as source/drain contacts. As the IGZO thickness decreases, the threshold shifts towards positive gate voltage, due to an easier depletion of the thinner IGZO layer.

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Graphene has also been used to change the contact properties between the IGZO layer and the metal electrode. In [243] a tunneling-contact SGT with a graphene interlayer between amorphous IGZO and Ti electrodes was reported (figure 22). In [244] a graphene monolayer was applied to create Schottky contacts with Ti electrodes. This graphene monolayer formed an effective potential barrier of 0.2 eV. In these graphene-tunnel SGTs the SS temperature dependence decreased as the drain current was increased. This suggests that the dominant electron transport mechanism changes from TE to quantum tunneling.

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Bottom up emerging technologies, which have great potential for high performance computing, are often hampered by technological challenges. For 2D materials, one such challenge is the large contact resistance. For SWCNT devices, it is the realization of arrays containing only semiconducting nanotubes. The relaxation of the performance metrics due to such challenges provides these technologies possible applications in ubiquitous electronics. Here, we discuss briefly some of the ways that have been investigated.

A new class of nanocomposite TFTs have emerged in the past twenty years based on thin films of chemically synthesized nanomaterials. The basic constituent can be thin films of nanocrystals, nanowires or nanotubes. The electronic transport resembles neither that in the nanomaterial, nor transport in the bulk, but is typically dominated by the transport between nano-objects and can be described by percolation models [246]. Nanonet TFTs [247] are a fascinating topic and have been the subject of a recent review [79], although for most materials the source/drain contacts do not play an important role in the transport.

Nevertheless, it is important to mention the emerging field of TFT transistors fabricated using carbon nanotube networks. CNT TFTs can broadly be grouped into those where the channel length is about or greater than the tube length, of relevance here, and those where the channel length is much smaller, which were discussed in previous section 2.2. While aligned nanotube arrays or single devices typically have mobilities exceeding 2500 cm² V⁻¹ s⁻¹, the mobility of such thin-film transistors is ∼20–500 cm² V⁻¹ s⁻¹ due to the tube-tube interactions. In these nanonet-type TFTs, the contacts at the film/source or film/drain interfaces can still play an important role either by introducing an important barrier to transport [248], or by increasing the off-state current through the ambipolar transport at the drain at higher voltages [249]. Pecunia's group has shown how the ambipolar devices can be used in ultra-low power electronics [250]. CNT TFTs have been used to realize a modern microprocessor [149] with CMOS devices and channel lengths down to 1.5 μm. To the best of our knowledge these are the highest-performing TFT computing devices demonstrated.

The SB height of CNTFETs can be strongly influenced by changing its environment (from air to vacuum), where the barrier height is strongly affected by molecular adsorption (of water and oxygen in particular) both on the metal and on the CNT [251]. Electrochemical reactions at the SiO₂/nanotube interface in the presence of water and oxygen were also shown to play a significant role on the electron/hole current balance [252]. Such effects have been used to develop chemical sensors [253] and biosensors [254]

Like carbon nanotubes, SBs in 2D materials also exhibit very unique properties. The SB height (SBH) and Fermi-level pinning exhibit a thickness-dependent phenomenon [243], providing an exciting playground for engineering nanodevices and novel sensors. This is reminiscent of the observation that the Richardson constant changes with film thickness, as discussed in section 1.2. For large work-function metals, p-type SB contacts have been shown to be more favorable. This thickness dependence provides a parameter to manipulate the SBH in metal-2D semiconductor interfaces, illustrated by the SBHs in table 1. Research on 2D materials has focused on realizing transistors and explorations in ubiquitous electronics are just beginning to emerge. Sensor-based technology for health and the environment also have been developed to take advantage of the ability to control the SB [255]. Another field of application related to the ambipolar nature of the contacts is reconfigurable transistors for secure circuits, as discussed at the end of the next section.

Table 1. The SBH ${\phi }_{{\rm{B}}}^{e}(n)$ of the nth MoS₂ layer in a 7-layer AgMoS₂ junction. V_n−1,n is the energy difference between the conduction band minimum (CBM) in adjacent layers, which shows the depinning between MoS₂ layers. ${\phi }_{{\rm{B}}}^{e}(n)$ = CBM_n − E_F; V_n−1,n = CBM_n − CBM_n−1. (All values are given in eV). These calculated values are taken from [243].

nth MoS2 layer	${\phi }_{{\rm{B}}}^{e}(n)$	Vn−1,n
1st	0.14	—
2nd	0.30	0.16
3rd	0.42	0.12
4th	0.52	0.10
5th	0.56	0.04
6th	0.57	0.03
7th	0.58	0.01

SBMOSFET devices with mid-gap SBs and intrinsic or low-doped Si have a considerable SB for both electrons and holes., [80]. These devices have an SB for both electrons and holes, delivering an ambipolar transfer characteristic, i.e. allowing for the injection of both electrons and holes for positive and negative gate voltages respectively as shown in figure 23(a). This behavior differs significantly from that described above. Figure 23(b) shows the calculated transfer characteristics from TCAD simulations. NiS₂/Si junctions were modeled and both TE and tunneling transport were taken into account.

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To explain the underlying transport, band diagrams for such midgap aligned contacts are shown in figure 23. The transfer characteristics, plotted in a semi-logarithmic representation, generally exhibit two distinct regions below threshold voltage, which are separated by a characteristic kink: (a) a steeper and linearly increasing one for low drain currents and (b) a shallower and progressively saturating region at higher drain currents. As indicated by TCAD simulations, for I_d the predominant injection mechanism is, in region (a), TE and in region (b) thermally assisted field emission (TFE). Kedzierski and Knoch [59, 256] showed that the TE region generally has a steeper SS than the tunneling dominated (TFE) region. In the TE case the potential barrier maximum is displaced linearly by the acting gate field as in a conventional MOSFET. However, in the case where TFE is dominant, the bands at the injecting junction drop below the SB height so that the barrier maximum remains fixed and only the thickness of the SB and thus the tunneling probability is modulated, delivering typically shallower SSs. As a result, the magnitude of the threshold voltage is substantially increased compare to that of conventional MOSFETs. Both the ambipolarity and the threshold voltage degradation of Schottky FETs can be addressed by manipulating the potential across the active region through the application of independently gated regions, as shown in section 3.5 for reconfigurable nanowire transistors.

Ambipolar SB MOSFETs have also been demonstrated with NiSi₂/intrinsic Si nanowires following the injection mechanism [162] described in figure 23. Both the ambipolarity and the threshold voltage degradation of Schottky FETs, as discussed in section 1.3, can be addressed by manipulating the potential across the active region through the application of independently gated regions, as discussed next for reconfigurable transistors.

Reconfigurable transistors (RFETs) are an emerging type of device family based on Schottky source and drain junctions applied to an ultrathin-body semiconductor (1D or 2D) that are capable of delivering unipolar p- and n-channel MOSFET functionality as deterministically selected by an electric signal. A complete review of the transport properties, device types and emerging circuit applications can be found in [257–259]. To define the device polarity, RFETs are able to filter out a specific unwanted polarity of charge carriers by the introduction of a potential barrier within the active region. A dedicated gate electrode commonly labeled as the polarity gate (PG) is employed to control this barrier, whereas the charge carrier flow is regulated by an additional electrode, the control gate (CG). Different RFET realizations exist; in the simplest embodiment, the two independent gates are positioned to directly overlap the SB junctions, deliberately defining the CG and PG. The gated Schottky diodes allow respectively for efficient injection control at the source [260, 261] and for polarity adjustment at the drain by blocking the injection of the undesired carrier type, see figures 24(a)–(c). This 'dual gated' RFET approach was realized in heterogeneously integrated Si nanowires with intruded NiSi₂ contacts [12, 262], Ge nanowires with Ni_x Ge_1−x [263] and Al electrodes [264], as well as in Si_x Ge_(1−x) nanosheets with Al contacts [166]. In addition to its geometric simplicity and doping-free fabrication flow, the device exhibits a very low static power consumption, with gate induced drain lowering-like leakage suppressed even for higher source-drain bias. Nevertheless, the threshold voltage remains comparatively high for the same reason as in single gated SBFETs.

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To improve the SS, a second RFET embodiment called here the 'triple gate' RFET can be found in the literature. It employs three independently gated regions [164, 265–272]. Therein, both SB junctions are steered with the same potential as the PG that defines the predominant charge carrier type, while the 'middle segment' of the channel is itself steered by the CG, see figures 24(d)–(f). Since the potential at the SB junctions are decoupled from the CG by the shielding action of the PG, the subthreshold behavior is governed by the barrier maximum within the CG-steered segment, as in a conventional MOSFET. Compared to the 'dual gated' RFET, the 'triple gate' one has a higher static power consumption in the off state. Both RFET realizations however show smaller on currents than MOSFETs and therefore have a longer switching delay. The targeted applications are thus in the field of low standby and low operation power applications. Performance enhancement with respect to Si is expected with the use of Ge channels [271, 273] as TE and TAT become more efficient due to the smaller SB heights and smaller effective tunneling masses.

The benefit of RFETs becomes visible when the inherent reconfiguration feature is exploited at runtime to enable fine-grained reconfigurable circuits. Generic logic gates and circuits can thereby alter their functionality at runtime, e.g. between NAND/NOR/MIN [274] or XOR/XNOR/MAX [269], reducing overall chip area consumption [275] and enabling new opportunities for camouflaging circuits for hardware security applications [276, 277], as well as embedded electronics.

Some 2D materials exhibit ambipolarity where the SB or electrostatic gating can allow either p-type or n-type transport. This was first exploited to realize electrostatically reversible polarity using a dual top gates [278] and then complex logic gates [279] in MoTe₂. More recently these ideas were extended too demonstrate more complex circuits and neuromorphic functionality [280], secure applications [272] and reconfigurable logic integrated with optoelectronic transistors [281].

As temperature is reduced in crystalline semiconductors, the mobility of carriers increases significantly due to a reduction in phonon scattering. This effect gives rise to an increasing 'on' current and in Si transistors continues until about 100 K. Concomitantly, the number of carriers decreases exponentially, giving rise to an increase in the threshold voltage and a sharper SS, as shown in figure 25. Below 100 K, the majority of carriers are frozen out and various interesting physical phenomena can be observed, such as weak and strong localization, phase transitions, universal conductance fluctuations, Coulomb blockade and resonant tunneling through impurities. Such effects are seen in SBMOSFETs, but in addition the SB plays an important role in the transport. As the temperature is reduced from 300 K, current transport mechanisms across the Schottky junctions become decreasingly dominated by thermal processes until they are dominated by direct tunneling, as in Schottky diodes [9]. The dominant scattering mechanism in the mK temperature range and at low bias voltages is electron–electron interactions [283], which can give rise to a zero-bias anomaly [284]. The dopants in silicon can be frozen out [285], but the advantage of the SB device is that carriers in the metallic contacts (as opposed to non-degenerately doped source-drain ones) are not. For SBMOSFETs with relatively large widths, the SB can also be used to energetically isolate a single or small number of dopants, allowing a rich exploration of physics [286–289]. Figure 25 shows characteristics at 300 K and 4 K of an SBMOSFET device with PtSi contacts, which have a critical temperature T_c ≃ 0.8 K for film thicknesses above 20 nm [290]. At room temperature, the SS follows the expected thermally activated law and differs only minimally from the ideal 60 mV dec^–1, revealing a good control of the channel carrier density.

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At 4 K, I_on changes from 10 to 6 nA at a V_ds = 100 μV, and the SS becomes steeper (though less than expected at 4 K). These observations indicate that the transport is limited by the source/drain contacts. At very low voltages, the observed small reproducible oscillations can be attributed to the Coulomb blockade of residual dopants that are either in the channel [291] or near the source/drain contacts [287].

Interesting and different characteristics are observed if the metallic contacts become superconducting. Superconductivity is a macroscopic quantum phenomenon, in which a phonon-mediated pair-wise attractive interaction between electrons causes a large fraction of the Fermi sea to condense into a lower-energy state [292, 293]. It causes the opening of a symmetric gap around the Fermi level in the energy spectrum and at T = 0 K, it has a magnitude of 2Δ ≈ 3.53k_B T_c [292]. The energy scales important here are much smaller than those typically encountered in semiconductor physics: the superconducting gap Δ ranges from 3 × 10⁻⁴ eV (Al) to 3 × 10⁻³ eV (Nb), the most commonly used superconductors for the devices of interest here [294], and superconducting devices operate at temperatures 3–5 orders of magnitude below room temperature. When k_B T ≪ Δ, the transfer of individual carriers from the semiconducting channel to the superconducting contacts is forbidden by the gap in the superconducting single-particle energy spectrum.

Transport is possible however, through a process called Andreev reflection [295], in which an incident electron from the normal material picks up an additional electron at the interface and continues as a Cooper pair inside the superconductor, while the resulting hole precisely traces back the incoming particle's path on the normal side [295–297]. The resulting 'leaking' of the superconductivity into the normal metal is referred to as the proximity effect, and induces a smaller minigap inside the channel [298, 299]. Figure 26 shows that at temperatures well below the superconducting transition of PtSi, the differential conductance exhibits a clear dip at zero V_d bias followed by symmetrical peaks around V_d = ±160 μV. The insert of figure 26 shows how the voltage at which the peaks appear evolves with temperature: It follows the expected reduction of the superconducting energy gap [292], represented by the solid line, from which we can extract the superconducting transition temperature T_c = 0.67 K of the PtSi contacts. The device essentially has two superconducting/semiconducting (S/Sm) interfaces in series, such that the peak position V_peak should be twice the superconducting gap. Extrapolated to zero temperature, V_peak = 0.163 mV, which differs by 20% from the value expected from the BCS relationship Δ = 3.5k_B T_c/q [292, 300]. This theoretical gap value corresponds to the gap deep inside the superconducting material, and can be different at the S/Sm interface due to the proximity effect.

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The rate at which Andreev reflection occurs, depends strongly on the interface transparency of the S/Sm interface and the height of the SB [301], which is why these measurements were performed with sufficiently large V_g to be in the 'on' state of the transistor. Since the coherence of the Andreev pair also depends on scattering within the channel, a large V_bg was applied as well. If the retro-reflected hole can propagate in the channel and be itself retro-reflected as an electron at the second S/Sm interface, then this closed loop will generate a bound (Andreev) state that can carry a supercurrent, causing the conductance to diverge, as illustrated in figure 27.

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If the coherence of the Andreev pairs is strong enough such that the Josephson coupling E_J = ℏ I_c/2e, where I_c is the critical current, is greater than the thermal energy k_B T, then the semiconducting channel will act as the weak link in a Josephson junction [303]. At this point, the probability of the Andreev pair entering the superconductor on the other side would depend on the phase difference between the two condensates [299, 304]. Once a Josephson coupling is established, the coherent transport creates a zero-resistance channel [305–307] such that a current can be applied without generating a source-drain voltage (the DC Josephson effect, see figure 27(b)), while an applied voltage will cause the current to oscillate (the AC Josephson effect) [308]. Note that the device in figure 26 exhibits a decrease of the conductance at zero bias, implying that the quality of the interface is not good enough to observe Josephson tunneling. Nevertheless, the fact that the conductance stays finite at zero bias, indicates that transparency is partially achieved.

If superconductivity can be transmitted through the semiconducting channel of SBMOSFETs with superconducting source/drain electrodes, then a Josephson FET (JoFET) is realized, where the modulation of the carrier density in the channel and SB height can control the critical current [303, 309]. It has been demonstrated that a semiconducting channel with high transparency to the superconducting leads can be used to provide a tunable Josephson coupling for superconducting qubits [310, 311]. Semiconducting channels that are small enough to behave as quantum dots have revealed a rich variety of charging phenomena [312]. Devices with larger [313], metallic channels no longer exhibit the Josephson effect, but the superconducting gap can be used to extract the hot tail of the Fermi–Dirac distribution and thus locally reduce the electron temperature [314].

This research area has recently become sufficiently mature to be of industrial interest; quantum supremacy was achieved in a superconducting system in 2019 [315], and several industrial laboratories have now published roadmaps towards quantum computers with millions of qubits [316–318]. The Josephson junctions on which these devices are built provide a dissipationless nonlinear inductance to a circuit that can be approximated as an LC resonator with quantized excitations. The nonlinearity ensures that the spacings between successive energy levels are different (i.e. the system becomes anharmonic), such that the lowest two can be isolated as an effective two-level system and serve as a qubit. Control of the interactions between multiple qubits requires the tuning of either the resonance frequencies of these circuits themselves, or that of a coupler placed between two fixed-frequency qubits. This tuning is accomplished by varying the inductance, most commonly by running a current through a nearby line to apply a magnetic flux to a superconducting quantum interference device (SQUID) made up of a pair of Josephson junctions. Alternative designs have been demonstrated where nanowire-based JoFETs replace these flux-modulated SQUID loops, creating gate-tunable transmons that rely on a static voltage instead of a continuous current [310, 311], with the advantages of reduced dissipation, cross talk, and flux noise. Lithography-based two-dimensional JoFETs [319, 320] provide the additional benefit of easier scaling, and fit in the trend of integrating CMOS technologies such as 3D routing with through-silicon vias (TSVs) and multi-level wiring in quantum circuits [321].

These experiments have typically been realized with academic fabrication techniques such as aluminum lift-off[312], electron-beam lithography of the junction areas [322], or the use of materials such as InAs and GaAs [323]. It remains to be seen if a modern transistor could be modified to perform the same tasks, and if so, what precisely would have to be changed for it to perform optimally [302]. Such mass-manufacturable JoFETs could have a large impact especially in the fast-growing field of superconducting qubits.

FETs are typically optimized for large on/off current ratios, short switching times, low energy dissipation and small footprint. Most of these concerns are irrelevant for JoFET applications. In a superconducting qubit, the supercurrent is varied by only a few percent during operation to change the Josephson coupling [310] and large on/off ratios are not essential. Concerning the switching times and low energy dissipation, in a JoFET the capacitance of the junction itself is far smaller than that of the qubit to which it provides the inductance, and therefore the LC time $\tau =\sqrt{\mathrm{LC}}$ to discharge the channel is guaranteed to be short enough for qubit control. The superconducting state of the circuit ensures that RC times are zero, and that dissipation is minimal even at high frequencies. The fabrication of JoFETs instead seeks to realize devices with critical currents on the order of tens of nA [310], few two-level systems [324, 325], little quasiparticle tunneling [326], and low sensitivity to flux noise in the channel or charge noise on the gate electrode. Apart from the last requirement, which is less stringent in the today's most common type of superconducting qubit [327], these aims are all helped by increasing the supercurrent density of the JoFET, as we now discuss.

For the phase information of the superconducting condensate in one lead to be coherently transmitted to the other, a few processes need to occur successively. First, Andreev reflection requires that both the incoming and outgoing particles tunnel through any potential barriers present between the superconductor and semiconductor. A good intuition for this process can be gained by considering the WKB approximation for the tunneling of a particle. If we assume, for simplicity, a square barrier potential of height ϕ and width d, we find that an incoming electron has a transmission probability (transparency) ${ \mathcal T }\approx \exp \left(-d\sqrt{8{m}^{\star }\phi }/\hslash \right)$, which for an undressed electron with m^⋆ = m_e, a barrier of height ϕ = 0.1 eV and width d = 1 nm, equals roughly ${ \mathcal T }\approx 0.1$. Since the reflected hole would have to traverse the same region, we naively expect that the entire process of Andreev reflection occurs with probability $P={{ \mathcal T }}^{2}\approx 0.01$ (a more comprehensive calculation based on the BTK formalism [301] would find $P\approx 0.35{{ \mathcal T }}^{2.1}$ when ${ \mathcal T }=0.1$). The salient point here is that Andreev reflection is exponentially suppressed by an increase in SB height, with about twice as a large an exponent as a single-particle tunneling process, making it critically important to obtain a transparent interface, as in section 1.3

Once Andreev reflection has occurred, an effective energy gap ${{\rm{\Delta }}}_{\mathrm{Sm}}^{0}=\delta \,{\rm{\Delta }}$ will be induced on the semiconducting side of the interface, where Δ is the gap in the bulk superconductor and δ the factor by which it is reduced (δ ∝ T² in the above approximation). The Andreev pair then has to traverse the channel, during which the electron and hole will dephase due to accumulated differences in energy, and finally a second reflection needs to take place in order to enter the opposing lead. Intuitively, one may expect that the critical current of the junction, which is proportional to the combined likelihood of this entire string of events, would scale as δ² and drop exponentially with the length of the channel [305, 306],

$$\begin{eqnarray}&&{I}_{{\rm{c}}}\propto {\delta }^{2}\,{e}^{-L/{\xi }_{\mathrm{Sm}}},\end{eqnarray} \tag{ 9 }$$

where ξ_Sm is an effective coherence length for the Andreev pair inside the semiconductor. Although this exponential decay is an accurate depiction of thermal effects [303, 328, 329] when we replace ${\xi }_{\mathrm{Sm}}\to {L}_{{\rm{T}}}=\sqrt{{\hslash }D/2\pi {k}_{{\rm{B}}}T}$, where D = v_F ℓ_e/3 is the diffusion constant, it does not fully capture the physics of longer channels. For diffusive junctions (L ≫ ℓ_e), the relevant energy scale for the proximity effect turns out to be the Thouless energy E_Th = ℏ D/L² [330, 331], where E_Th/ℏ is the rate at which single charges diffuse across the channel [307]. Unless the superconducting gap Δ is smaller than E_Th, this diffusion rate will then limit the supercurrent that can cross the channel (before thermal effects are taken into account), as is shown in figure 28. We can thus summarize the zero-temperature behavior as:

$$\begin{eqnarray}&&{I}_{{\rm{c}}}\propto {\delta }^{2}\,{\rm{\Delta }}\quad (\mathrm{short}),\ \mathrm{or}\qquad {I}_{{\rm{c}}}\propto {\delta }^{2}\,{E}_{\mathrm{Th}}\quad (\mathrm{long}),\end{eqnarray} \tag{ 10 }$$

where the dependence of δ on the barrier strength at the interface is described by the BTK model [301]. Depending on how the thermal energy k_B T compares to Δ and E_Th, a finite temperature can then be accounted for with a further factor that ranges from ${e}^{-L/{L}_{T}}$ to ${T}^{3/2}{e}^{-L/{L}_{T}}$ [307, 332].

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These limits to the critical current can be directly translated to guidelines for the design of a good Schottky barrier JoFET (SBJoFET), which are illustrated in figure 29. The main concerns are: (a) to ensure a low barrier between the contacts and the channel, which can be achieved by using materials with good lattice matching, similar effective electron mass, clean interfaces and low SBs. Note that the SB lowering described in figure 2, should significantly aid the latter as channel lengths are made smaller; (b) The effective channel length may be reduced by downscaling the device and increasing its mobility, which could possibly bring it into the ballistic regime; finally, (c) if the Thouless energy is of the same order, or even larger than the superconducting gap of the contact material, further improvements in performance could be gained by using a higher critical temperature of the superconducting contacts.

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III-V materials have long been the preferred semiconductors in mesoscopic superconductivity experiments thanks to their higher mobility and the absence of carrier freeze-out at low temperatures [303, 333]. A few years after a gate-tunable proximity effect was detected as a voltage-dependent resistance jump in a Pb/p-InAs/Pb junction [334, 335], it was demonstrated that tunable coherent transport across the entire channel could also be obtained in shorter junctions [336]. The largest supercurrents to date, and some of the most transparent interfaces to semiconducting channels, have been obtained using InAs nanowires [337, 338], which became an especially attractive platform for quantum applications after sub-gap states were further suppressed by epitaxially growing the superconducting aluminum layer [339, 340]. Lithographically defined structures in planar heterostructures containing InAs films were later proposed to allow for easier fabrication of larger circuits that contain multiple junctions [319, 320]. Now, as the demand for scalability grows [341], it is natural to ask whether some of the technologies honed for MOSFET development can be put to use in this field, and whether silicon could be a viable substrate.

In fact, around the same time that it was shown in InAs [336], a gated supercurrent was demonstrated in a 200 nm long, highly doped Si channel contacted by a superconducting Pb alloy [342]. It is possible that the freeze-out of carriers was prevented by the high doping level of 5 × 10¹⁸ cm⁻³, and the channel may have been further populated by field emission from the superconducting leads, allowed by the overlap of the gate with the source and drain electrodes [333]. Members of the same group later contributed to demonstrating a self-aligned Si MOSFET with doped source/drain regions underneath superconducting Nb electrodes [322]. This device was closer to a conventional doped source/drain FET than an SBMOSFET due to the doping level of 5 × 10¹⁹ cm⁻³ underneath the superconducting contacts, without an overlap between the gate and the superconducting electrodes.

An SBJoFET could be formed instead by replacing the doped source/drain regions in this type of device by superconducting silicides, which would have several likely advantages. As discussed in section 1.3 and suggested by lower capacitance ratios [61], a significant part of the transport in an SBMOSFET occurs further away from the oxide/semiconductor interface compared to conventional MOSFETs. This should reduce surface scattering, improving the mean free path in the channel. Mobility could be further improved by reducing the channel doping, which due to the presence of SBs in the off state would no longer create the risk of short-channel effects. It is however not yet clear how well JoFETs with low doping or undoped Si would perform. Earlier demonstrations of Josephson coupling through silicon weak links used extremely high doping of 1 × 10²⁰ cm⁻³ [343, 344] (corresponding to 0.2 at%) in order to boost the coherence length [345], but only devices with lower channel doping levels of 5 × 10¹⁸ cm⁻³ [342] and 5 × 10¹⁶ cm⁻³ [322] have exhibited electrostatic gating.

The use of silicides in SBMOSFETs can also provide greater control over the channel length, which can be reduced below the lithographically defined gate length by the encroachment of the metallic alloy underneath the spacers during silicidation. If this process is allowed to continue until the silicide extends beneath the gate electrode, it may enhance SBJOFET operation by significantly reducing the SB height via the image charge. This would ensure a large variation in critical current, and more importantly, provide control over the interface transparency, the main bottleneck to obtaining a Josephson coupling in JoFETs as highlighted in figure 29. Experiments on junctions with InGaAs weak links have shown that a gate effect can be used to suppress SBs up to the point that Andreev reflection dominates transport across the interface [346]. These InGaAs devices had higher doping close to the superconducting contacts [347], placing them between the doped source/drain FET and Schottky FET architectures. Such intermediate devices can also be constructed in CMOS technology by out-diffusing dopants from the source/drain regions, which provides additional control over the SB and may further improve the capacitance ratio [63]. With these options available, and more than three decades of technological progress in semiconductor manufacturing since the first demonstration of a silicon JoFET, we can be optimistic that SBMOSFETs optimized for quantum applications are within technological reach.