Synthesizable Verilog Code Generator for Variable-Width Tree Multipliers

Tree multipliers are fast multipliers which are important for timing-critical applications. However, due to the irregular multiplier structure, the process of coding a tree multiplier is often very time-consuming. In addition, it is difficult to generalize the multiplier codes for variable-width inputs. In this paper, the authors used Python scripts to generate Verilog codes for tree multipliers automatically in a very short amount of time, by specifying only the required data width. The generated tree multiplier designs are synthesized and implemented using TSMC 180nm technology as well as Artix-7 FPGA. Through analysis, it is observed that modified Booth multiplier designed with Dadda tree reduction algorithm has up to 47% smaller area and up to 71% shorter delay compared to array multiplier. All multiplier designs are thoroughly simulated and functionally verified.