Development of an Image Fringe Zero Selection System for Structuring Elements with Stereo Vision Disparity Measurements

When performing image operations involving Structuring Element (SE) and many transforms it is required that the outside of the image be padded with zeros or ones depending on the operation. This paper details how this can be achieved with simulated hardware using DSP Builder in Matlab with the intention of migrating the design to HDL (Hardware Description Language) and implemented on an FPGA (Field Programmable Gate Array). The design takes few resources and does not require extra memory to account for the change in size of the output image.