Abstract
The protection of superconducting magnets is a very important issue and demanding challenge in the LHC and other superconducting accelerating facilities. The quench phenomenon can destroy components of the accelerator, and therefore this digital system was designed, implemented, tested, and installed near each superconducting magnet in the LHC tunnel. The quench detection principle relies on the extraction of resistive voltage by compensation of the inductive part of the voltage. This article presents briefly the architecture applied to the design and the validation of the FPGA-based quench detector for the main quadrupoles of the LHC. The article focusses on digital design with the use of FPGA by VHDL coding and on the verification by simulation. The design is a replacement for the old detection system.
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