CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

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Published 28 November 2012 Published under licence by IOP Publishing Ltd
, , Citation P Carniti et al 2012 JINST 7 P11026 DOI 10.1088/1748-0221/7/11/P11026

1748-0221/7/11/P11026

Abstract

The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

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10.1088/1748-0221/7/11/P11026