Ultrascaled Double-Gate Monolayer ${\mathrm{Sn}\mathrm{S}}_{2}$ MOSFETs for High-Performance and Low-Power Applications

Ultrascaled Double-Gate Monolayer ${Sn S}_{2}$ MOSFETs for High-Performance and Low-Power Applications

Shiying Guo, Yangyang Wang, Xuemin Hu, Shengli Zhang, Hengze Qu, Wenhan Zhou, Zhenhua Wu, Xuhai Liu, and Haibo Zeng

Phys. Rev. Applied 14, 044031 – Published 19 October 2020

Abstract

The shrinking of field-effect transistors (FETs) is in great demand for next-generation integrated circuits. However, traditional silicon FETs are reaching the scaling limits, and it is therefore urgent to explore alternative paradigms. Two-dimensional (2D) materials attract great research enthusiasm, owing to their abilities to suppress short-channel effects. Herein, we evaluate the electronic properties and device performance of ultrascaled 2D ${Sn S}_{2}$ metal-oxide-semiconductor FETs (MOSFETs) via ab initio simulations. Specifically, the $I_{on}$ value of the 5.5 nm monolayer ${Sn S}_{2}$ n-MOSFETs is ultrahigh, up to 3400 µA/µm, as a result of the small effective masses of the conduction-band minimum of monolayer ${Sn S}_{2}$ . Until the channel length is scaled down to 4 nm, the MOSFETs can fulfill the standards of $I_{on}$ , delay time, and power dissipation product of the International Roadmap for Devices and Systems (IRDS) 2018 goals for high-performance devices. Moreover, the 5.5 nm monolayer ${Sn S}_{2}$ n-MOSFETs can also fulfill the IRDS 2018 requirements for the 2028 horizon for low-power applications. This work demonstrates that monolayer ${Sn S}_{2}$ is a favorable channel material for future competitive ultrascaled devices.

Received 28 May 2020
Revised 27 July 2020
Accepted 14 September 2020

DOI:https://doi.org/10.1103/PhysRevApplied.14.044031

Physics Subject Headings (PhySH)

Ballistic transport Electronic materials Electronic structure Quantum transport

Field-effect transistors Transition metal dichalcogenides

Density functional calculations Nonequilibrium Green's function

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Shiying Guo¹, Yangyang Wang², Xuemin Hu¹, Shengli Zhang ^1,†, Hengze Qu¹, Wenhan Zhou ¹, Zhenhua Wu ³, Xuhai Liu⁴, and Haibo Zeng ^1,*

¹MIIT Key Laboratory of Advanced Display Materials and Devices, School of Materials Science and Engineering, Nanjing University of Science and Technology, Nanjing 210094, China
²Nanophotonics and Optoelectronics Research Center, Qian Xuesen Laboratory of Space Technology, China Academy of Space Technology, Beijing 100094, China
³Key Laboratory of Microelectronics Device and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
⁴College of Microtechnology & Nanotechnology, Qingdao University, Qingdao 266071, China

^*zeng.haibo@njust.edu.cn
^†zhangslvip@njust.edu.cn

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Vol. 14, Iss. 4 — October 2020

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Figure 1
(a) Top and lateral views of the atomic structure of monolayer ${Sn S}_{2}$ . Lattice parameter (a = b) is 3.70 Å. (b) Schematics of Brillouin zones for monolayer ${Sn S}_{2}$ . (c) Band structure of monolayer ${Sn S}_{2}$ by PBE functional. Inset: three-dimensional band structure near the Fermi level. Band-decomposed charge-density distributions corresponding to (d) conduction-band minimum (CBM) and (e) valence-band maximum (VBM) of monolayer ${Sn S}_{2}$ . Isovalue is 0.003 e/bohr³.
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Figure 2
Schematic view and transfer characteristics of monolayer ${Sn S}_{2}$ MOSFETs along (a) MΓ and (b) MK directions for HP applications, with V_DS = 0.64 V, several channel lengths (L_ch), U (underlap) = 0 nm, and dielectric thickness t_ox= 0.41 nm. Optimized electrode doping concentration is 5 × 10¹³ cm⁻².
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Figure 3
Comparison of LDOS and spectral current of the n-type MΓ-direction monolayer ${Sn S}_{2}$ MOSFETs under V_DS = 0.64 V. 5.5-nm-channel-length FETs at (a) V_g = −0.3 V for off state and (b) V_g = 0.34 V for on state. 3.1-nm-channel-length FETs at (c) V_g = −0.3 V and (d) 0.34 V. In the LDOS, µ_S and µ_D represent the electrochemical potential of the source and drain, respectively, and are marked by the gray dotted line in the spectral current. Yellow arrows imply thermionic and tunneling electron transport, white dotted line is the conduction-band edge (E_c), and Φ_B is the energy barrier for electrons.
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Figure 4
Transmission spectra of monolayer ${Sn S}_{2}$ MOSFETs under V_DS = 0 V, with 5.5 and 5.3 nm channel lengths at V_g = 0 V, with different electrode doping concentrations (N_e).
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Figure 5
(a) Optimal on-state current (I_on) versus gate length (L_g) around 5 nm for monolayer ${Sn S}_{2}$ and other 2D MOSFETs materials in HP applications [31, 32, 33, 34, 46, 51, 52]. Gray dashed line at I_on = 923 µA/µm corresponds to represent IRDS 2018 requirements for HP applications for the year 2028. (b) Power-delay product (PDP) versus intrinsic delay time (τ) for monolayer ${Sn S}_{2}$ and other 2D MOSFET materials in HP applications [32, 33, 34, 46, 52, 53]. Gray solid lines represent specific energy-delay product (EDP).
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Figure 6
Schematic view and transfer characteristics of monolayer ${Sn S}_{2}$ MOSFETs along (a) MΓ and (b) MK directions for LP applications, with V_DS = 0.64 V, several channel lengths, and t_ox= 0.41 nm. Optimized electrode doping concentration is 3 × 10¹³ cm⁻². (c) Optimal I_on versus L_g around 5 nm for monolayer ${Sn S}_{2}$ and other 2D MOSFET materials in LP applications [31, 32, 33, 34, 55, 56]. Gray dashed line at I_on= 520 µA/µm corresponds to IRDS 2018 requirements for LP applications for the year 2028. (d) PDP versus τ for monolayer ${Sn S}_{2}$ and other 2D MOSFETs materials in LP applications [32, 33, 34, 56]. Gray solid lines represent specific EDP.
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Physical Review Applied

Ultrascaled Double-Gate Monolayer SnS2 MOSFETs for High-Performance and Low-Power Applications

Shiying Guo, Yangyang Wang, Xuemin Hu, Shengli Zhang, Hengze Qu, Wenhan Zhou, Zhenhua Wu, Xuhai Liu, and Haibo Zeng

Phys. Rev. Applied 14, 044031 – Published 19 October 2020

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Ultrascaled Double-Gate Monolayer ${Sn S}_{2}$ MOSFETs for High-Performance and Low-Power Applications