• Open Access

Spiderweb Array: A Sparse Spin-Qubit Array

Jelmer M. Boter, Juan P. Dehollain, Jeroen P.G. van Dijk, Yuanxing Xu, Toivo Hensgens, Richard Versluis, Henricus W.L. Naus, James S. Clarke, Menno Veldhorst, Fabio Sebastiano, and Lieven M.K. Vandersypen
Phys. Rev. Applied 18, 024053 – Published 19 August 2022

Abstract

One of the main bottlenecks in the pursuit of a large-scale–chip-based quantum computer is the large number of control signals needed to operate qubit systems. As system sizes scale up, the number of terminals required to connect to off-chip control electronics quickly becomes unmanageable. Here, we discuss a quantum-dot spin-qubit architecture that integrates on-chip control electronics, allowing for a significant reduction in the number of signal connections at the chip boundary. By arranging the qubits in a two-dimensional array with about 12μm pitch, we create space to implement locally integrated sample-and-hold circuits. This allows us to offset the inhomogeneities in the potential landscape across the array and to globally share the majority of the control signals for qubit operations. We make use of advanced circuit modeling software to go beyond conceptual drawings of the component layout, to assess the feasibility of the scheme through a concrete floor plan, including estimates of footprints for quantum and classical electronics, as well as routing of signal lines across the chip using different interconnect layers. We make use of local demultiplexing circuits to achieve an efficient signal-connection scaling, leading to a Rent’s exponent as low as p=0.43. Furthermore, we use available data from state-of-the-art spin qubit and microelectronics technology development, as well as circuit models and simulations, to estimate the operation frequencies and power consumption of a million-qubit array. This work presents a complementary approach to previously proposed architectures, focusing on a feasible scheme to integrating quantum and classical hardware, and identifying remaining challenges for achieving full fault-tolerant quantum computation. It thereby significantly closes the gap towards a fully CMOS-compatible quantum computer implementation.

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  • Received 6 October 2021
  • Revised 19 January 2022
  • Accepted 5 May 2022

DOI:https://doi.org/10.1103/PhysRevApplied.18.024053

Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.

Published by the American Physical Society

Physics Subject Headings (PhySH)

Condensed Matter, Materials & Applied PhysicsQuantum Information, Science & Technology

Authors & Affiliations

Jelmer M. Boter1,2, Juan P. Dehollain1,2,3, Jeroen P.G. van Dijk1,2,4, Yuanxing Xu1,2, Toivo Hensgens1,2, Richard Versluis1,5, Henricus W.L. Naus1,5, James S. Clarke6, Menno Veldhorst1,2, Fabio Sebastiano1,4, and Lieven M.K. Vandersypen1,2,6,*

  • 1QuTech, Delft University of Technology, Lorentzweg 1, Delft 2628 CJ, Netherlands
  • 2Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, Delft 2628 CJ, Netherlands
  • 3School of Mathematical and Physical Sciences, University of Technology Sydney, Ultimo, NSW 2007, Australia
  • 4Department of Quantum and Computer Engineering, Delft University of Technology, Delft 2628 CJ, Netherlands
  • 5Netherlands Organization for Applied Scientific Research (TNO), P.O. Box 155, Delft 2600 AD, Netherlands
  • 6Components Research, Intel Corporation, 2501 NE Century Blvd, Hillsboro, Oregon 97124, USA

  • *l.m.k.vandersypen@tudelft.nl

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Vol. 18, Iss. 2 — August 2022

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