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Stress analysis for fracturing potential of blind via in a build‐up substrate

Tong Hong Wang (Stress‐Reliability Laboratory, Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan, Republic of China)
Yi‐Shao Lai (Stress‐Reliability Laboratory, Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan, Republic of China)

Circuit World

ISSN: 0305-6120

Article publication date: 1 May 2006

298

Abstract

Purpose

The submodeling technique is incorporated in a finite element analysis to investigate the stress state of blind vias of different structural configurations.

Design/methodology/approach

The test vehicle is a multi‐chip module plastic ball grid array comprised of a four‐layer build‐up substrate. The calculated displacement field from the global model for the entire package is interpolated on the boundaries of the submodel, which involved the detailed structure of a blind via structure. Through the analysis, the potential of fracturing on the blind via is examined.

Findings

From the analysis it was found that filled blind vias in general have a smaller potential for delamination compared to the unfilled ones. Moreover, symmetric blind via layouts with a blind via located at the center of the through hole appear to be the most appropriate design for this particular test vehicle.

Originality/value

The value of the paper lies in its ability to provide insights into the prevention of fracturing of blind vias in a build‐up substrate through a novel numerical analysis using the submodeling technique.

Keywords

Citation

Hong Wang, T. and Lai, Y. (2006), "Stress analysis for fracturing potential of blind via in a build‐up substrate", Circuit World, Vol. 32 No. 2, pp. 39-44. https://doi.org/10.1108/03056120610642897

Publisher

:

Emerald Group Publishing Limited

Copyright © 2006, Emerald Group Publishing Limited

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