Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Jesus Ruiz-Amaya; Manuel Delgado-Restituto; J. Francisco Fernandez-Bootello; Jose M. de la Rosa

doi:10.1117/12.608286

30 June 2005 Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Jesus Ruiz-Amaya, Manuel Delgado-Restituto, J. Francisco Fernandez-Bootello, Jose M. de la Rosa

Proceedings Volume 5837, VLSI Circuits and Systems II; (2005) https://doi.org/10.1117/12.608286
Event: Microtechnologies for the New Millennium 2005, 2005, Sevilla, Spain

Abstract

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm² die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

Citation Download Citation

Jesus Ruiz-Amaya, Manuel Delgado-Restituto, J. Francisco Fernandez-Bootello, and Jose M. de la Rosa "Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications", Proc. SPIE 5837, VLSI Circuits and Systems II, (30 June 2005); https://doi.org/10.1117/12.608286

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KEYWORDS

Switching

Transistors

Switches

Distortion

Power supplies

Binary data

Computer aided design

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