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Low Temperature Poly-Si TFTs Using Solid Phase Crystallization of Very Thin Films and an Electron Cyclotron Resonance Chemical Vapor Deposition Gate Insulator

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Copyright (c) 1991 The Japan Society of Applied Physics
, , Citation Thomas W. Little et al 1991 Jpn. J. Appl. Phys. 30 3724 DOI 10.1143/JJAP.30.3724

1347-4065/30/12S/3724

Abstract

Low temperature (T≦600°C) polycrystalline silicon thin film transistors (poly-Si TFTs) have been fabricated by solid phase crystallization (SPC) of amorphous silicon (a-Si) films deposited by low pressure chemical vapor deposition (LPCVD). These TFTs are distinguished by the very thin nature of the channel Si layer (25 nm) and the use of an SiO2 gate insulator deposited by electron cyclotron resonance chemical vapor deposition (ECR-CVD). The present process eliminates the need for hydrogenation and produces mobilities greater than 20 cm2/V·s and on/off current ratios greater than 107.

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10.1143/JJAP.30.3724