High-Performance Buried-Gate Surrounding Gate Transistor for Future Three-Dimensional Devices

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Published 8 October 2004 Copyright (c) 2004 The Japan Society of Applied Physics
, , Citation Makoto Iwai et al 2004 Jpn. J. Appl. Phys. 43 6904 DOI 10.1143/JJAP.43.6904

1347-4065/43/10R/6904

Abstract

We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

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