Abstract
The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments and simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in the four states and thus on read schemes for detecting the four Vth's. It is also shown that the read scheme can be selected by controlling DIBL using device parameters including gate length, injected charge fraction, and injected charge density. Suitable read schemes for low-voltage and low-power applications are discussed.