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Virtualizing Transactional Memory

Published:01 May 2005Publication History
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Abstract

Writing concurrent programs is difficult because of the complexity of ensuring proper synchronization. Conventional lock-based synchronization suffers from wellknown limitations, so researchers have considered non-blocking transactions as an alternative. Recent hardware proposals have demonstrated how transactions can achieve high performance while not suffering limitations of lock-based mechanisms. However, current hardware proposals require programmers to be aware of platform-specific resource limitations such as buffer sizes, scheduling quanta, as well as events such as page faults, and process migrations. If the transactional model is to gain wide acceptance, hardware support for transactions must be virtualized to hide these limitations in much the same way that virtual memory shields the programmer from platform-specific limitations of physical memory. This paper proposes Virtual Transactional Memory (VTM), a user-transparent system that shields the programmer from various platform-specific resource limitations. VTM maintains the performance advantage of hardware transactions, incurs low overhead in time, and has modest costs in hardware support. While manysystem-level challenges remain, VTM takes a step toward making transactional models more widely acceptable.

References

  1. {1} H. Akkary, R. Rajwar, and S. T. Srinivasan. Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. In Proceedings of the 36th International Symposium on Microarchitecture, December 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. {2} C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded Transactional Memory. In Proceedings of the Eleventh International Symposium on High-Performance Computer Architecture, February 2005. Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. {3} B. H. Bloom. Space/Time Trade-Offs in Hash Coding with Allowable Errors. Communications of the ACM, 13(7), 1970. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. {4} A. Chang and M. Mergen. 801 Storage: Architecture and Programming. ACM Transactions on Computer Systems, 6(1), February 1988. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. {5} K. P. Eswaran, J. Gray, R. A. Lorie, and I. L. Traiger. The Notions of Consistency and Predicate Locks in a Database System. Communications of the ACM, 19(11), November 1976. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. {6} L. Fan, P. Cao, J. Almeida, and A. Z. Broder. Summary Cache: A Scalable Wide-Area Web Cache Sharing Protocol. IEEE/ACM Transactions on Networks, 8(3), 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. {7} L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. {8} T. Harris and K. Fraser. Language Support for Lightweight Transactions. In Object-Oriented Programming, Systems, Languages, and Applications, October 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. {9} M. Herlihy, V. Luchangco, M. Moir, and W. N. Scherer. Software Transactional Memory for Dynamic-Sized Data Structures. In Proceedings of the Twenty-Second Annual Symposium on Principles of Distributed Computing, July 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. {10} M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In Proceedings of the 20th Annual International Symposium on Computer Architecture, May 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. {11} E. H. Jensen, G. W. Hagensen, and J. M. Broughton, A New Approach to Exclusive Data Access in Shared Memory Multiprocessors. Lawrence Livermore National Laboratory, Technical Report UCRL-97663, November 1987.Google ScholarGoogle Scholar
  12. {12} T. Kilburn, D. B. J. Edwards, M. J. Lanigan, and F. H. Sumner. One-Level Storage System. IRE Trans. Electronic Computers, 11(2), April 1962.Google ScholarGoogle Scholar
  13. {13} T. F. Knight. An Architecture for Mostly Functional Languages. In Proceedings of ACM Lisp and Functional Programming Conference, August 1986. Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. {14} L. Lamport. Concurrent Reading and Writing. Communications of the ACM, 20(11), November 1977. Google ScholarGoogle ScholarDigital LibraryDigital Library
  15. {15} D. E. Lowell and P. M. Chen. Free Transactions with Rio Vista. In Proceedings of the Sixteenth ACM Symposium on Operating Systems Principles, October 1997. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. {16} M. M. K. Martin, D. J. Sorin, H. W. Cain, M. D. Hill, and M. H. Lipasti. Correctly Implementing Value Prediction in Microprocessors That Support Multithreading or Multiprocessing. In Proceedings of the 34th International Symposium on Microarchitecture , December 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. {17} K. E. Moore, Thread-Level Transactional Memory. presented at Wisconsin Industrial Affiliates Meeting, October 2004 http://www.cs.wisc.edu/multifacet/papers/affiliates04_tltm.pdfGoogle ScholarGoogle Scholar
  18. {18} M. Prvulovic, M. J. Garzarán, L. Rauchwerger, and J. Torrellas. Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization. In Proceedings of the 28th Annual International Symposium on Computer Architecture, June 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. {19} R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Proceedings of the 34th International Symposium on Microarchitecture , December 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. {20} R. Rajwar and J. R. Goodman. Transactional Lock-Free Execution of Lock-Based Programs. In Proceedings of the Tenth Symposium on Architectural Support for Programming Languages and Operating Systems, October 2002. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. {21} M. V. Ramakrishna. Practical Performance of Bloom Filters and Parallel Free-Text Searching. Communications of the ACM, 32(10), 1989. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. {22} M. Satyanarayanan, H. H. Mashburn, P. Kumar, D. C. Steere, and J. J. Kistler. Lightweight Recoverable Virtual Memory. ACM Transactions on Computer Systems, 12(1), 1994. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. {23} S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler. Scalable Hardware Memory Disambiguation for High ILP Processors. In Proceedings of the 36th International Symposium on Microarchitecture, December 2003. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. {24} N. Shavit and D. Touitou. Software Transactional Memory. In Proceedings of the 14th ACM Symposium on Principles of Distributed Computing, August 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. {25} G. S. Sohi, S. E. Breach, and T. N. Vijaykumar. Multiscalar Processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, June 1995. Google ScholarGoogle ScholarDigital LibraryDigital Library
  26. {26} J. M. Stone, H. S. Stone, P. Heidelberger, and J. Turek. Multiple Reservations and the Oklahoma Update. IEEE Parallel & Distributed Technology, 1(4), November 1993. Google ScholarGoogle ScholarDigital LibraryDigital Library

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              • Published in

                cover image ACM SIGARCH Computer Architecture News
                ACM SIGARCH Computer Architecture News  Volume 33, Issue 2
                ISCA 2005
                May 2005
                531 pages
                ISSN:0163-5964
                DOI:10.1145/1080695
                Issue’s Table of Contents
                • cover image ACM Conferences
                  ISCA '05: Proceedings of the 32nd annual international symposium on Computer Architecture
                  June 2005
                  541 pages
                  ISBN:076952270X

                Copyright © 2005 Authors

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                Association for Computing Machinery

                New York, NY, United States

                Publication History

                • Published: 1 May 2005

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