Aline Mello
Ney Calazans
Fernando Moraes
ABSTRACT
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congestion in NoCs reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The goal of this work is to describe the implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in NoCs. One way to reduce congestion is to multiplex a physical channel using virtual channels (VCs). VCs reduce latency and increase network throughput. The insertion of VCs also enables to implement policies for allocating the physical channel bandwidth, which enables to support quality of service (QoS) in applications. This paper has two main contributions. The first is the detailed implementation of a NoC router with a parameterizable number of VCs. The second is the evaluation of latency and throughput in reasonably sized instances of the Hermes NoC (8x8 mesh), with and without VCs. Additionally, the paper compares the features of the proposed router with others employing VCs. Results show that NoCs with VCs accept higher injections rates w.r.t. NoCs without VCs, with a small standard deviation in the latency values, guaranteeing precise packet latency estimation.
- International Sematech. "International Technology Roadmap for Semiconductors - 2002" Update, 2002. Available at http://public.itrs.net.Google Scholar
- Martin, G.; Chang, H. "System on Chip Design". In: 9th International Symposium on Integrated Circuits, Devices & Systems, Tutorial 2, 2001.Google Scholar
- Kumar, S.; Jantsch, A.; Soininen, J. P.; Fonsell, M. "A Network on Chip Architecture and Design Methodology". In: Computer Society Annual Symposium on VLSI, 2002. Google ScholarDigital Library
- Benini, L.; De Micheli, G. "Powering networks on chips: energy-efficient and reliable interconnect design for SoCs". In: 14th International Symposium on Systems Synthesis, 2001, pp. 33--38. Google ScholarDigital Library
- Guerrier. P.; Greiner. A. "A generic architecture for on-chip packet-switched interconnections". In: Design Automation and Test in Europe (DATE'00), 2000, pp. 250--256. Google ScholarDigital Library
- Rijpkema, E.; et al. "A Router Architecture for Networks on Silicon". In: PROGRESS'2001.Google Scholar
- Dally, W. J. "Virtual-Channel Flow Control". In: 17th International Symposium on Computer Architecture, 1990, pp. 60--68. Google ScholarDigital Library
- Marescaux, T.; et al. "Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs". In: 12th Conference on Field-Programmable Logic and Applications, 2002, pp. 795--805. Google ScholarDigital Library
- Dally, W. J.; Towles, B. "Route Packets, Not Wires: On-chip Interconnection Networks". In: Design Automation Conference, 2001, pp. 684--689. Google ScholarDigital Library
- Goossens, K.; et al. "Guaranteeing the Quality of Service in Networks on Chip". Nurmi, J.; Tenhunen, H.; Isoaho, J.; Jantsch, A., editors, Networks on Chip, Kluwer 2003, pp. 61--82. Google ScholarDigital Library
- Kavaldjiev, N.; Smit, G.; Jansen, P. "Two Architectures for On-chip Virtual Channel Router". PROGRESS, 2004, pp. 96--102.Google Scholar
- Bolotin E. et al. "QNoC: QoS architecture and design process for network on chip". Journal of Systems Architecture, 50(2-3), Feb. 2004, pp. 105--128. Google ScholarDigital Library
- Bertozzi, D.; Benini, L. "Xpipes: A Network-on-chip Architecture for Gigascale Systems-on-Chip". IEEE Circuits and Systems Magazine, 4(2), 2004, pp. 18--31.Google ScholarCross Ref
- Yum, K. H.; Kim, E. J.; Das, C.R.; Yousif, M.; Duato, J. "Integrated Admission and Congestion Control for QoS Support in Clusters". In: IEEE International Conference on Cluster Computing, 2002, pp. 325--352. Google ScholarDigital Library
- Chuang, S.-T.; Goel, A.; Mckeown, N.; Prabhakar, B. "Matching output queuing with a combined input output queued switch". IEEE Journal on Selected Areas in Communications, 17(6), 1999, pp.1030--1039. Google ScholarDigital Library
- Dally, W. J.; Towles, B. "Principles and Practices of Interconnection Networks". San Francisco: Morgan Kaufmann, 2004, 550 p. Google ScholarDigital Library
- Moraes, F.; et al. "Hermes: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip". Integration the VLSI Journal, 38(1), Oct. 2004, pp. 69--93. Google ScholarDigital Library
- Glass, C.; Ni, L. "The Turn Model for Adaptive Routing". Journal of the Association for Computing Machinery, 41(5), Sep. 1994, pp. 874--902. Google ScholarDigital Library
- Duato, J.; Yalamanchili, S.; Ni, L. "Interconnection Networks". Elsevier Science, 2002, 600 p. Google ScholarDigital Library
Index Terms
- Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Recommendations
Virtual channels vs. multiple physical networks: a comparative analysis
DAC '10: Proceedings of the 47th Design Automation ConferencePacket-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange ...
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA
AbstractThe network-on-chip (NoC) has emerged as an efficient and scalable communication fabric for chip multiprocessors (CMPs) and multiprocessor system on chips (MPSoCs). The NoC architecture, the routers micro-architecture and links influence the ...
Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers
Special Issue on SPAA 2012Packet-switched network-on-chip (NoC) has provided a scalable solution to the communications for tiled multicore processors. However, the virtual channel (VC) buffers in the NoC consume significant dynamic and leakage power. To improve the energy ...
Comments