Kevin Camera
ABSTRACT
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the user's design which allow the system to be monitored and updated at runtime. An assortment of logic is added before synthesis to allow variable buffering, assertion checking, and automatic breakpointing. Low-level clock control and access to off-chip storage is managed by a custom hardware operating system. Through the addition of these features, a system can be debugged directly on the hardware, bypassing simulation and reducing iterations through the design flow.
- C. Chang, K. Kuusilinna, B. Richards, A. Chen, N. Chan, R. W. Brodersen, and B. Nikolić. Rapid design and analysis of communication systems using the BEE hardware emulation environment. In Proc. IEEE Rapid System Prototyping Workshop, June 2003. Google Scholar
Digital Library
- C. Chang, J. Wawrzynek, and R. W. Brodersen. BEE2: A high-end reconfigurable computing system. IEEE Design and Test of Computers, 22(2):114--125, Mar. Apr. 2005. Google ScholarDigital Library
- P.-Y. Chung, Y.-M. Wang, and I. N. Hajj. Logic design error diagnosis and correction. IEEE Transactions on VLSI Systems, 2(3):320--332, Sept. 1994.Google ScholarDigital Library
- V. K. Garg. Observation and control for debugging distributed computations. In Proc. Third International Workshop on Automatic Debugging (AADEBUG), volume 2 of Linköping Electronic Articles in Computer and Information Science, pages 1--12, May 1997.Google Scholar
- B. Peischl and F. Wotawa. Modeling state in software debugging of VHDL-RTL designs -- A model-based diagnosis approach. In Proc. Fifth International Workshop on Automated and Algorithmic Debugging (AADEBUG), pages 197--210, Sept. 2003.Google Scholar
- H. K.-H. So. BORPH: An OS for reprogrammable hardware. http://bwrc.eecs.berkeley.edu/People/Grad_Students/skhay/BORPH.Google Scholar
- J. Tombs, M. A. Aguirre Echanóve, F. Muñoz, V. Baena, A. Torralba, A. Fernandez-León, and F. Tortosa. The implementation of a FPGA hardware debugger system with minimal system overhead. In Proc. Field Programmable Logic and its Applications (FPL), volume 3203 of Lecture Notes in Computer Science, pages 1062--1066, Aug. 2004.Google Scholar
- M. G. Valderas, E. de la Torre, F. Ariza, and T. Riesgo. Hardware and software debugging of FPGA based microprocessor systems through debug logic insertion. In Proc. Field Programmable Logic and its Applications (FPL), volume 3203 of Lecture Notes in Computer Science, pages 1057--1061, Aug. 2004.Google Scholar
- Xilinx, Inc. ChipScope Pro Software and Cores User Guide, Feb. 2005. http://www.xilinx.com/ise/optional_prod/cspro.htm.Google Scholar
Index Terms
- An integrated debugging environment for reprogrammble hardware systems
Recommendations
An integrated debugging environment for FPGA computing platforms
FPGA '08: Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arraysLarge-scale, direct-mapped FPGA computing systems are traditionally very difficult to debug due to the high level of parallelism and limited access to internal signal values. This poster describes our solution to this problem, in which the concepts of ...
Hardware/software co-debugging for reconfigurable computing
HLDVT '00: Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)Application development environments for reconfigurable computing are the topic of many research and development projects yet few comprehensive debugging tools have been provided. In this paper we describe a debugging environmental use with FPGA ...
Stepwise Debugging for Hardware Accelerators
ASPLOS 2023: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2High-level programming models for hardware design let domain experts quickly produce specialized accelerators. However, tools for debugging these accelerators remain tied to low-level hardware description languages (HDLs). High-level descriptions ...
Comments