H. Kadota
- 1.e.g.K. Hwang and F. A. Briggs, Computer Architecture and Parallel Processing, McGraw-Hill, New York, 1984. Google Scholar
Digital Library
- 2.H. Kadota et al., "VLSI Parallel Computer with Data Transfer Network: ADENA," Proc. 1989 Int'l. Conf. on Parallel Proc., 1989, pp. 1-319-322.Google Scholar
- 3.K. Kaneko et al., "A VLSI RISC with 20MFLOPS Peak, 64bit Floating Point Unit," IEEE J. Solid-State Cir., Vol.24 No.5 pp.1331-1340, Oct., 1989.Google ScholarCross Ref
- 4.Y. Nakakura et al., "A Versatile Data Transfer Control Unit for a Parallel Processor System," Dig. 1989 Symp. on VLSI Circuits, pp.13-14Google Scholar
- 5.e.g.D.P. Bertsekas and J. N. Tsitsiklis, Parallel And Distributed Computation, Prentice-Hall NJ 1989., pp.158-166 Google ScholarDigital Library
- 6.T. Nogi, "Parallel Computation," Studies in Mathematics and Its Applications, No.18, North-Holland, Amsterdam, pp.279-318, 1986Google Scholar
- 7.S. Odanaka et al, "3dim.Device Simulation on a Super Parallel Computer: ADENA," Proc. 7th VLSI Process/Device Modeling Workshop, pp.122-125, Aug., 1990.Google Scholar
- 8.K. Murata, T. Oguni and Y. Karaki, Super Computer (written in Japanese) Maruzen, Tokyo 1985, pp.149-153Google Scholar
Index Terms
- Parallel computer ADENART—its architecture and application
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