Maher Mneimneh
Karem Sakallah
ABSTRACT
Determining the depth of sequential circuits is a crucial step towards the completeness of bounded model checking proofs in hardware verification. In this paper, we formulate sequential depth computation as a logical inference problem for Quantified Boolean Formulas. We introduce a novel technique to simplify the complexity of the constructed formulas by applying simple transformations to the circuit netlist. We also study the structure of the resulting simplified QBFs and construct an efficient SAT-based algorithm to check their satisfiability. We report promising experimental results on some of the ISCAS 89 benchmarks.
- A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu, "Symbolic Model Checking Using SAT Procedures instead of BDDs," in 36th Design Automation Conference, 1999.]] Google Scholar
Digital Library
- A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic Model Checking without BDDs," in TACAS'99, 1999.]] Google ScholarDigital Library
- R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," in IEEE Transactions on Computers, 35(8), pp. 677--691, August 1986.]] Google ScholarDigital Library
- J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic Model Checking for Sequential Circuit Verification," in IEEE Transactions on Computer-Aided Design of Integrated Circuits 13(4), pp. 401--424, April 1994.]]Google ScholarDigital Library
- E. M. Clarke, E. A. Emerson, and A. P. Sistla, "Automatic Verification of Finite-state Concurrent Systems Using Temporal Logic Specifications," in ACM Transactions on Programming Languages and Systems, 8(2), pp. 244--263, 1986.]] Google ScholarDigital Library
- A. Gupta, Z. Yang, P. Ashar, L. Zhang, and S. Malik, "Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs," in Proceedings of the International Conference on Computer-Aided Design, 2001.]] Google ScholarDigital Library
- M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT solver," in Proceedings of the Design Automation Conference, 2001.]] Google ScholarDigital Library
- D. A. Plaisted, A. Biere, and Y. Zhu, "A Satisfiability Procedure for Quantified Boolean Formulae," submitted for publication, Discrete Applied Mathematics.]] Google ScholarDigital Library
- M. Sheeran, S. Singh, and G. Stalmarck, "Checking Safety Properties Using Induction and a SAT-solver," in Formal Methods in Computer Aided Design, 2000.]] Google ScholarDigital Library
- C.-C. Yen, K.-C Chen, and J.-Y. Jou, "A Practical Approach to Cycle Bound Estimation for Property Checking," in 11th IEEE/ACM International Workshop on Logic Synthesis, pp. 149--154, June 2002.]]Google Scholar
- SAT-based sequential depth computation
Recommendations
Enhancing SAT-based sequential depth computation by pruning search space
GLSVLSI '09: Proceedings of the 19th ACM Great Lakes symposium on VLSIThe sequential depth determines the completeness of bounded model checking in design verification. Recently, a SAT-based method is proposed to compute the sequential depth of a design by searching the state space. Unfortunately, it suffers from the ...
A modular CNF-based SAT solver
SBCCI '10: Proceedings of the 23rd symposium on Integrated circuits and system designThe state-of-the-art SAT solvers, such as Chaff [11], zChaff [18], BerkMin [5], and Minisat [2] usually share the same core techniques, for instance: the watched literals structures conflict clause recording and non-chronological backtracking. ...
Solving SAT and SAT Modulo Theories: From an abstract Davis--Putnam--Logemann--Loveland procedure to DPLL(T)
We first introduce Abstract DPLL, a rule-based formulation of the Davis--Putnam--Logemann--Loveland (DPLL) procedure for propositional satisfiability. This abstract framework allows one to cleanly express practical DPLL algorithms and to formally reason ...
Comments