ABSTRACT
As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Further, the threshold voltage scales nonlinearly, raising the ratio of the threshold voltage to the supply voltage and making the voltage (IR) drop in the power/ground (P/G) network a serious problem in modern IC design. Traditional P/G network analysis methods are often very computationally expensive, and it is thus not feasible to co-synthesize P/G network with floorplan. To make the co-synthesis feasible, we need not only an efficient, effective, and flexible floorplanning algorithm, but also a very efficient, yet sufficiently accurate P/G network analysis method. In this paper, we present a method for floorplan and P/G network co-synthesis based on an efficient P/G network analysis scheme and the B*-tree floorplan representation. We integrate the co-synthesis into a commercial design flow to develop an effective power integrity (IR-drop) driven design methodology. Experimental results based on a real-world circuit design and the MCNC benchmarks show that our design methodology successfully fixes the IR-drop errors earlier at the floorplanning stage and thus enables the single-pass design convergence.
- Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. B*-trees: A new representation for non-slicing floorplans. In Proc. of DAC, pages 458--463, 2000. Google ScholarDigital Library
- H. Chen, C.-K. Cheng, A. B. Kahng, M. Mori, and Q. Wang. Optimal planning for mesh-based power distribution. In Proc. of ASP-DAC, pages 444--449. IEEE Press, 2004. Google ScholarDigital Library
- T.-H. Chen and C. C.-P. Chen. Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods. In Proc. of DAC, pages 559--562. ACM Press, 2001. Google ScholarDigital Library
- S. Chowdhury. Optimum design of reliable ic power networks having general graph topologies. In Proc. of DAC, pages 787--790. ACM Press, 1989. Google ScholarDigital Library
- T. T. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. MIT Press, 1990. Google ScholarDigital Library
- A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan, B. Tutuianu, and D. Bearden. Design and analysis of power distribution networks in PowerPC microprocessors. In Proc. of DAC, pages 738--743. ACM Press, 1998. Google ScholarDigital Library
- G. H. Golub and V. L. Charles F. Matrix Computations. Johns Hopkins University Press, 1996.Google Scholar
- P.-N. Guo, C.-K. Cheng, and T. Yoshimura. An O-tree representation of non-slicing floorplan and its applications. In Proc. of DAC, pages 268--273. ACM Press, 1999. Google ScholarDigital Library
- D. Kouroussis and F. N. Najm. A static pattern-independent technique for power grid voltage integrity verification. In Proc. of DAC, pages 99--104. ACM Press, 2003. Google ScholarDigital Library
- J. N. Kozhaya, S. R. Nassif, and F. N. Najm. Multigrid-like technique for power grid analysis. In Proc. of ICCAD, pages 480--487. IEEE Press, 2001. Google ScholarDigital Library
- OpenRISC project, http://www.opencores.org/.Google Scholar
- J.-M. Lin, H.-E. Yi, and Y.-W. Chang, Module placement with boundary constraints using B*-trees, in IEE Proceedings--Circuits, Devices and Systems, Vol. 149, No. 4, pp. 251--256, August 2002. (EI/SCI)Google ScholarCross Ref
- S. Lin and N. Chang. Challenges in power-ground integrity. In Proc. of ICCD, pages 651--654. IEEE Press, 2001. Google ScholarDigital Library
- V. Litovski and M. Zwolinski. VLSI Circuit Simulation and Optimization. Chapman & Hall, 1997.Google Scholar
- J. Singh and S. S. Sapatnekar. Topology optimization of structured power/ground networks. In Proc. of ISPD, pages 116--123. ACM Press, 2004. Google ScholarDigital Library
- Source code, http://cc.ee.ntu.edu.tw/~ywchang/research.html.Google Scholar
- K. Wang and M. Marek-Sadowska. On-chip power supply network optimization using multigrid-based technique. In Proc. of DAC, pages 113--118. ACM Press, 2003. Google ScholarDigital Library
- S.-W. Wu and Y.-W. Chang. Efficient power/ground network analysis for power integrity-driven design methodology. In Proc. of DAC, pages 177--180. ACM Press, 2004. Google ScholarDigital Library
- J.-S. Yim, S.-O. Bae, and C.-M. Kyung. A floorplan-based planning methodology for power and clock distribution in ASICs. In Proc. of DAC, pages 766--771. ACM Press, 1999. Google ScholarDigital Library
Index Terms
- Floorplan and power/ground network co-synthesis for fast design convergence
Recommendations
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence
As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the power wire increase substantially. Furthermore, the threshold voltage scales nonlinearly, raising the ratio of the threshold ...
Handling routability in floorplan design with twin binary trees
As technology moves into the deep-submicron era, the complexities of VLSI circuits grow rapidly. Interconnect optimization has become an important concern. Most routability-driven floorplanners [H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. ...
Modern floorplanning based on fast simulated annealing
ISPD '05: Proceedings of the 2005 international symposium on Physical designUnlike classical floorplanning that usually handles only block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die (outline) and additionally considers the packing with block positions and ...
Comments