skip to main content
10.1145/1146909.1147098acmconferencesArticle/Chapter ViewAbstractPublication PagesdacConference Proceedingsconference-collections
Article

Mining global constraints for improving bounded sequential equivalence checking

Published:24 July 2006Publication History

ABSTRACT

In this paper, we propose a novel technique on mining relationships in a sequential circuit to discover global constraints. In contrast to the traditional learning methods, our mining algorithm can find important relationships among several nodes efficiently. The nodes involved may often span several time-frames, thus improving the deductibility of the problem instance. Experimental results demonstrate that the application of these global constraints to SAT-based bounded sequential equivalence checking can achieve one to two orders of magnitude speedup. In addition, because it is orthogonal to the underlying SAT solver, it can help to enhance the efficacy of typical SAT based verification flows.

References

  1. M. H. Schulz, E. Trischler and T. M. Sarfert. SOCRATES: A highly efficient automatic test pattern generation system. IEEE Trans. CAD, vol. 7, no. 1, Jan. 1988, pp. 126--137.Google ScholarGoogle ScholarDigital LibraryDigital Library
  2. W. Kunz and D. K. Pradhan. Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. CAD, vol. 12, no. 5, May 1993, pp. 684--694.Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. H. Ichihara and K. Kinoshita. On acceleration of logic circuits optimization using implication relations. In Proc. Asian Test Symp., 1997, pp. 222--227. Google ScholarGoogle ScholarDigital LibraryDigital Library
  4. W. Kunz, D. Stoffel and P. R. Menon. Logic optimization and equivalence checking by implication analysis. IEEE Trans. CAD, Vol. 16 , no. 3, Mar. 1997, pp.266--281. Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. S. Kajihara, K. K. Saluja and S. M. Reddy. Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. Proc. European Test Symp., 2004, pp. 108--113. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. M. E. Amyeen, W. K. Fuch, I. Pomeranz and V. Boppana. Implication and evaluation techniques for proving fault equivalence. Proc. VLSI Test Symp., 1999, pp. 201--207. Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. W. Kunz, D. Pradhan and S. Reddy. A Novel Framework for Logic Verification in a Synthesis Environment. IEEE Trans. CAD, vol. 15, no. 1, Jan. 1996, pp. 20--32. Google ScholarGoogle ScholarDigital LibraryDigital Library
  8. M. lyer and M. Abramovici. FIRE: A Fault-independent Combinational Redundancy Identification Algorithm. IEEE Trans. VLSI Systems., vol. 4, no. 2, Jun. 1996, pp. 295--301. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. K. Zhao, M. Rudnick and J. Patel. Static Logic Implication with Application to Fast Redundancy Identification. Proc. VLSI Test Symp., 1997, pp. 288--293. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M. H. Schulz and E. Auth. Improved deterministic test pattern generation with applications to redundancy identification. IEEE Trans. CAD, vol. 8, no. 7, Jul. 1989, pp. 811--816.Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. Y. Novikov. Local search for Boolean relations on the basis of unit propagation, Proc. Design, Automation and Test in Europe Conf., 2003, pp. 810--815. Google ScholarGoogle ScholarDigital LibraryDigital Library
  12. J. Rajski and H. Kox. A Method to Calculate Necessary Assignments in ATPG. Proc. Int'l. Test Conf., 1990, pp. 25--34.Google ScholarGoogle Scholar
  13. S.T. Chakradhar and V. D. Agrawal. A transitive closure algorithm for test generation. IEEE Trans. CAD., 1993, pp. 1015 -- 1028.Google ScholarGoogle ScholarDigital LibraryDigital Library
  14. W. Kunz and D. K. Pradhan. Recursive Learning: A new Implication Technique for Efficient Solutions to CAD problems test, verification, and optimization. IEEE Trans. CAD., 1993, pp.1149--1158.Google ScholarGoogle Scholar
  15. J. Zhao, J. A. Newquist and J. Patel. A graph traversal based framework for sequential logic implication with an application to c-cycle redundancy identification. Proc. VLSI Design Conf., 2001, pp. 163--169. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. K. Gulrajani and M. S. Hsiao. Multi-node static logic implications for redundancy identification. Proc. Design, Automation, and Test in Europe Conf., 2000, pp. 729--733. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. M. Syal, R. Arora and M. S. Hsiao. Extended forward implications and dual recurrence relations to identify sequentially untestable faults. Proc. Int'l Conf. Computer Design, 2005, pp. 453--460. Google ScholarGoogle ScholarDigital LibraryDigital Library
  18. D. J. Hand, H. Mannila and P. Smyth. Principles of Data Mining. MIT Press, Aug. 2001. Google ScholarGoogle ScholarDigital LibraryDigital Library
  19. A. Biere, A. Cimatti, E. M. Clarke, M. Fujita and Y. Zhu Symbolic model checking using SAT procedures instead of BDDs. Proc. Design Automation Conf., 1999, pp. 317--320. Google ScholarGoogle ScholarDigital LibraryDigital Library
  20. A. Kuehlmann. Dynamic Transition Relation Simplification for Bounded Property Checking. Proc. Int. Conf. Computer-Aided Design., 2004, pp. 50--57. Google ScholarGoogle ScholarDigital LibraryDigital Library
  21. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang and S. Malik. Chaff: Engineering an efficient SAT solver. Proc. Design Automation Conf., 2001, pp. 530--535. Google ScholarGoogle ScholarDigital LibraryDigital Library
  22. E. Goldberg and Y. Novikov. BerkMin: A fast and robust Sat Solver. Proc. European Design and Test Conf., 2002, pp. 142--149. Google ScholarGoogle ScholarDigital LibraryDigital Library
  23. F. Lu, L. C. Wang and K. T. Cheng. A circuit SAT solver with signal correlation guided learning. Proc. European Design and Test Conf., 2003, pp. 892--897. Google ScholarGoogle ScholarDigital LibraryDigital Library
  24. R. Agrawal, T. Imielinski and A. Swami. Mining association rules between sets of items in large databases. Proc. Conf. Management of Data, 1993, pp. 207--216. Google ScholarGoogle ScholarDigital LibraryDigital Library
  25. R. Agrawal, T. Imielinski and A. Swami. Database mining: A performance perspective. IEEE Trans. Knowledge and Data Engineering, vol. 5, No. 6, 1993, pp. 914--925. Google ScholarGoogle ScholarDigital LibraryDigital Library

Index Terms

  1. Mining global constraints for improving bounded sequential equivalence checking

    Recommendations

    Comments

    Login options

    Check if you have access through your login credentials or your institution to get full access on this article.

    Sign in
    • Published in

      cover image ACM Conferences
      DAC '06: Proceedings of the 43rd annual Design Automation Conference
      July 2006
      1166 pages
      ISBN:1595933816
      DOI:10.1145/1146909

      Copyright © 2006 ACM

      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

      Publisher

      Association for Computing Machinery

      New York, NY, United States

      Publication History

      • Published: 24 July 2006

      Permissions

      Request permissions about this article.

      Request Permissions

      Check for updates

      Qualifiers

      • Article

      Acceptance Rates

      Overall Acceptance Rate1,770of5,499submissions,32%

      Upcoming Conference

      DAC '24
      61st ACM/IEEE Design Automation Conference
      June 23 - 27, 2024
      San Francisco , CA , USA

    PDF Format

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader