D. P. Rodohan
Abstract
Search of a state space is a common function in artificial intelligence applications consuming a large proportion of the total processing time. In this paper we propose a hierarchical architecture using content addressable memory to accelerate the A* algorithm in a Prolog system and remove the associated high memory overheads.
- [Ka87] DAP Prolog: A set-oriented approach to Prolog Kacsuk, P. et al Computer Journal Vol. 30, No. 5, pp. 393-403. 1987. Google Scholar
Digital Library
- [Nil80] Principles of Artificial Intelligence Nilsson, N.J. Morgan Kaufmann Publishers, Inc. 1980. Google ScholarDigital Library
- [Ogur87] A 20Kbit Associative Memory LSI for Artificial Intelligence Machines Ogura, T. et al IEEE Journal of Solid-State Circuits, Vol 24, No 4, pp 1014-1020, Aug 1989.Google ScholarCross Ref
- [Prl84] Heuristics: Intelligent Search Strategies for Computer Problem Solving Pearl, J. Addison-Wesley Publishing Co. 1984. Google ScholarDigital Library
- [Prl88] The Optimality of A* Pearl, J. & Dechter, R. Search in Artificial Intelligence Edited by Kanal, L. & Kumar, V. Springer-Verlag. 1988.Google Scholar
- [War83] An Abstract Prolog Instruction Set Warren, D.H.D. Technical Note 309, Artificial Intelligence Centre, Computer Science and Technology Division, SRI, Menlo Park, C.A. 1983.Google Scholar
Index Terms
- An overview of the A architecture for optimisation problems in a logic programming environment
Recommendations
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems
ICCAD '11: Proceedings of the International Conference on Computer-Aided DesignSpin-transfer torque random access memory (STT-RAM) is a fast, scalable, durable non-volatile memory which can be embedded into standard CMOS process. A wide range of write speeds from 1ns to 100ns have been reported for STT-RAM. The switching current ...
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies
Many new memory technologies are available for building future energy-efficient memory hierarchies. It is necessary to have a framework that can quickly find the optimal memory technology at each hierarchy level. In this work, we first build a circuit-...
A Two-Dimensional, Distributed Logic Architecture
The authors present a novel, very fine grain associative architecture. This architecture maintains both a high degree of flexibility and fine graininess. This is done by reducing each processor to an associative memory cell. Unlike other associative ...
Comments