Jarek Nieplocha
ABSTRACT
The resurgence of current and upcoming multithreaded architectures and programming models led us to conduct a detailed study to understand the potential of these platforms to increase the performance of data-intensive, irregular scientific applications. Our study is based on a power system state estimation application and a novel anomaly detection application applied to network traffic data. We also conducted a detailed evaluation of the platforms using microbenchmarks in order to gain insight into their architectural capabilities and their interaction with programming models and application software. The evaluation was performed on the Cray MTA-2 and the Sun Niagar.
- M. Cannataro, D. Talia, P. K. Srimani, Parallel data intensive computing in scientific and commercial applications, Parallel Computing, 5(28), 2002. Google Scholar
Digital Library
- W. Anderson et. al. Early Experience with Scientific Programs on the Cray MTA-2, SC'03. Google ScholarDigital Library
- J. Feo, D. Harper, et. al . ELDORADO. Proc. Computing Frontiers'2005. 2005. Google ScholarDigital Library
- R. Brightwell et. al. Initial Performance Evaluation of the Cray SeaStar Interconnect, HOTI'05. Google ScholarDigital Library
- P. Kongetira, K. Aingaran, and K. Olukotun, "Niagara: A 32- Way Multithreaded Sparc Processor," IEEE Micro, vol. 25, pp. 21--29, March/April, 2005 2005. Google ScholarDigital Library
- D.A. Bader, John Feo, "On the Architectural Requirements for Efficient Execution of Graph Algorithms," in ICPP, 2005, pp. 547--556. Google ScholarDigital Library
- T. Ungerer, B. Robi, and A. Jurij, "A survey of processors with explicit multithreading," ACM Comput. Surv., vol. 35, pp. 29--63, 2003. Google ScholarDigital Library
- A. Abur and A. G. Exposito, Power System State Estimation: Theory and Implementation, Marcel-Dekker, 2004.Google ScholarCross Ref
- J. Nieplocha, A. Marquez, V. Tipparaju, D. Chavarría-Miranda, R. Guttromson, H. Huang, Towards Efficient Power System State Estimators on Shared Memory Computers, Proc. IEEE Power Engineering Society General Meeting, Montreal, 2006.Google Scholar
- C. Scherrer, N. Beagley. Conditional Independence Modeling for Categorical Anomaly Detection. Proc. Joint Ann Meeting of the Interface and Classification Soc. N. America. 2005.Google Scholar
- A.W. Moore and Mary S. Lee, Cached Sufficient Statistics for Efficient Machine Learning with Large Datasets, Journal of Artificial Intelligence Research, 8, 1998. Google ScholarDigital Library
- B. Smith, Taking the Lead in HPC http://media.corporate ir.net/media_files/irol/98/98390/presentations/SC04_Final.pdf). 2004.Google Scholar
- J. McCalpin, STREAM Sustainable Memory Bandwidth in High Perf. Computers. http://www.cs.virginia.edu/stream.Google Scholar
- T. Wang. 64-bit Mix Function. http://www.concentric.net/~Ttwang/tech/inthash.htmGoogle Scholar
- J. Bull and D. O'Neill, "A microbenchmark suite for OpenMP 2.0," SIGARCH Comput. Archit. News, vol. 29, pp. 41--48, 2001. Google ScholarDigital Library
- D.A Bader and Kamesh Madduri. "Designing Multithreaded Algorithms for Breadth-First Search and st-connectivity of the Cray MTA-2", Proc. ICPP'06. 2006. Google ScholarDigital Library
- C. Scherrer, N. Beagley, J. Nieplocha, A. Marquez, J. Feo and D. Chavarria-Miranda. Probability Convergence in a Multithreaded Counting Application, to appear in 2007 Workshop on Multithreaded Architectures and Applications (MTAAP'07), March 2007.Google Scholar
Index Terms
- Evaluating the potential of multithreaded platforms for irregular scientific computations
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