Abstract
In this article, we provide a fresh viewpoint to the interactions between clock skew scheduling and delay insertion. A race-condition-aware (RCA) clock skew scheduling is proposed to determine the clock skew schedule by taking race conditions (i.e., hold violations) into account. Our objective is not only to optimize the clock period, but also to minimize heuristically the required inserted delay. Compared with previous work, our major contribution includes the following two aspects. First, our approach achieves exactly the same results, but has significant improvement in time complexity. Second, our viewpoint can be generalized to other sequential timing optimization techniques.
- Albrecht, C., Korte, B., Schietke, J., and Vygen, J. 1999. Cycle time and slack optimization for VLSI chips. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (San Jose, CA) 232--238. Google ScholarDigital Library
- Burns, S. M. 1991. Performance analysis and optimization of asynchronous circuits. Ph.D. thesis, California Institute of Technology, Pasadena, California. Google ScholarDigital Library
- Cormen, T. H., Leiserson, C. E., and Rivest, R. L. 1990. Introduction to Algorithms. McGraw-Hill, New York. Google ScholarDigital Library
- Deokar, R. B. and Sapatnekar, S. S. 1994. A graph-theoretic approach to clock skew optimization. In Proceedings of the IEEE International Symposium on Circuits and Systems 1 (London), 407--410.Google Scholar
- Fishburn, J. P. 1992. LATTIS: An iterative speedup heuristic for mapped logic. In Proceedings of the IEEE/ACM Design Automation Conference (Anaheim, CA), 488--491. Google ScholarDigital Library
- Fishburn, J. P. 1990a. A depth-decreasing heuristic for combinational logic. In Proceedings of the IEEE/ACM Design Automation Conference (Orlando, FL), 361--364. Google ScholarDigital Library
- Fishburn, J. P. 1990b. Clock skew optimization. IEEE Trans. Comput. 39, 7 (Jul.), 945--951. Google ScholarDigital Library
- Huang, S. H. and Nieh, Y. T. 2006. Synthesis of nonzero clock skew circuits. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 25, 6 (Jun.), 961--976. Google ScholarDigital Library
- Huang, S. H. and Nieh, Y. T. 2003. Clock period minimization of non-zero clock skew circuits. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (San Jose, CA), 809--812. Google ScholarCross Ref
- Kourtev, I. S. and Friedman, E. G. 2000. Timing Optimization through Clock Skew Scheduling. Kluwer Academic. Google ScholarDigital Library
- Leiserson, C. E. and Saxe, J. B. 1991. Retiming synchronous circuitry. Algorithmica 6, 1 (Jan.), 5--35.Google ScholarDigital Library
- Liu, X., Papaefthymiou, M. C., and Friedman, E. G. 2002. Retiming and clock scheduling for digital circuit optimization. IEEE Trans. Comput.-Aided Des. Integ. Circ. Syst. 21, 2 (Feb.), 184--203. Google ScholarDigital Library
- Maheshwari, N. and Sapatnekar, S. S. 1999. Timing Analysis and Optimization of Sequential Circuits. Kluwer Academic. Google ScholarDigital Library
- Maheshwari, N. and Sapatnekar, S. S. 1998. Efficient retiming of large circuits.IEEE Trans. Very Large Scale Integ. Syst. 6, 1 (Mar.), 74--83. Google ScholarDigital Library
- Neves, J. L. and Friedman, E. G. 1996. Optimal clock skew scheduling tolerant to process variation. In Proceedings of the IEEE/ACM Design Automation Conference (Las Vegas, NV), 623--628. Google ScholarDigital Library
- Papaefthymiou, M. C. 1998. Asymptotically efficient retiming under setup and hold constraints. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (San Jose, CA), 288--295. Google ScholarDigital Library
- Papaefthymiou, M. C. 1994. Understanding retiming through maximum average-delay cycles, Math. Syst. Theory 27, 1 (Jan.), 65--84. Google ScholarDigital Library
- Shenoy, N. V., Brayton, R. K., and Sangiovanni-Vincentelli, A. L. 1993. Minimum padding to satisfy short path constraints. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (Santa Clara, CA), 156--161. Google ScholarDigital Library
- Sundararajan, V., Sapatnekar, S. S., and Parhi, K. K. 1999. MARSH: Min-Area retiming with setup and hold constraints. In Proceedings of the IEEE/ACM International Conference on Computer Aided Design (San Jose, CA), 2--6. Google ScholarDigital Library
Index Terms
- Clock skew scheduling with race conditions considered
Recommendations
Race-condition-aware clock skew scheduling
DAC '05: Proceedings of the 42nd annual Design Automation ConferenceThe race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and delay insertion (for resolving the race conditions) may lead to further clock ...
Synthesis of nonzero clock skew circuits
It is well known that the clock skew can be exploited as a manageable resource to improve circuit performance. However, due to the limitation of race conditions, the optimal clock skew scheduling often does not achieve the lower bound of sequential ...
Delay insertion method in clock skew scheduling
ISPD '05: Proceedings of the 2005 international symposium on Physical designThis paper describes a delay insertion method that improves the efficiency of clock skew scheduling. Clock skew scheduling is performed on synchronous circuits in order to improve the performance of a circuit; most often by permitting the circuit to ...
Comments