Tuhina Samanta
ABSTRACT
The dominance of interconnect delay in VLSI circuit design is well-known. Construction of routing trees in recent times has to take care of the timing issues for faster design convergence. Thus there is immense scope of research in design and performance of interconnects. Our current work encompasses two aspects of this research. On one hand, we consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilize this framework for verifying the supremacy of the Elmore delay estimate for its high fidelity. In order to ensure accurate computation of fidelity, (i) we propose new statistically proven formulae for fidelity, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of Elmore delay over that of linear delay.
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Index Terms
- Revisiting fidelity: a case of elmore-based Y-routing trees
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