ABSTRACT
Currently multi-threaded C or C++ programs combine a single-threaded programming language with a separate threads library. This is not entirely sound [7].
We describe an effort, currently nearing completion, to address these issues by explicitly providing semantics for threads in the next revision of the C++ standard. Our approach is similar to that recently followed by Java [25], in that, at least for a well-defined and interesting subset of the language, we give sequentially consistent semantics to programs that do not contain data races. Nonetheless, a number of our decisions are often surprising even to those familiar with the Java effort:
We (mostly) insist on sequential consistency for race-free programs, in spite of implementation issues that came to light after the Java work.
We give no semantics to programs with data races. There are no benign C++ data races.
We use weaker semantics for trylock than existing languages or libraries, allowing us to promise sequential consistency with an intuitive race definition, even for programs with trylock.
This paper describes the simple model we would like to be able to provide for C++ threads programmers, and explain how this, together with some practical, but often under-appreciated implementation constraints, drives us towards the above decisions.
- S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993. Google ScholarDigital Library
- S. V. Adve and K. Gharachorloo. Shared memory consistency models: A tutorial. IEEE Computer, 29(12):66--76, 1996. Google ScholarDigital Library
- S. V. Adve and M. D. Hill. Weak ordering-A new definition. In Proc. 17th Intl. Symp. Computer Architecture, pages 2--14, 1990. Google ScholarDigital Library
- AMD Corp. AMD64 Architecture Programmer's Manual - Volume 2: System Programming, July 2007.Google Scholar
- D. Aspinall and J. Sevcik. Java memory model examples: Good, bad, and ugly. VAMP07 Proceedings http://www.cs.ru.nl/~chaack/VAMP07/, 2007.Google Scholar
- H. Boehm and N. Maclaren. Should volatile acquire atomicity and thread visibility semantics? C++ standards committee paper WG21/N2016 = J16/06-0086, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2016.html, April 2006.Google Scholar
- H.-J. Boehm. Threads cannot be implemented as a library. In Proc. Conf. on Programming Language Design and Implementation, 2005. Google ScholarDigital Library
- H.-J. Boehm. A less formal explanation of the proposed c++ concurrency memory model. C++ standards committee paper WG21/N2480 = J16/07-350, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2480.html, December 2007.Google Scholar
- H.-J. Boehm. Memory model rationales. C++ standards committee paper WG21/N2176 = J16/07-0036, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2176.html, March 2007.Google Scholar
- H.-J. Boehm. N2338: Concurrency memory model compiler consequences. C++ standards committee paper WG21/N2338=J16/07-198, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2338.htm, August 2007.Google Scholar
- H.-J. Boehm. N2392: A memory model for c++: Sequential consistency for race-free programs. C++ standards committee paper WG21/N2392=J16/07-252, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2392.htm, September 2007.Google Scholar
- H.-J. Boehm. Reordering constraints for pthread-style locks. In Proc. 12th Symp. Principles and Practice of Parallel Programming, pages 173--182, 2007. Google ScholarDigital Library
- H.-J. Boehm and L. Crowl. C++ atomic types and operations. C++ standards committee paper WG21/N2427=J16/07-0297, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2427.htm, October 2007.Google Scholar
- C++ Standards Committee, Pete Becker, ed. Working Draft, Standard for Programming Language C++. C++ standards committee paper WG21/N2461=J16/07-0331, http://www.open-std.org/JTC1/SC22/ WG21/docs/papers/2007/n2461.pdf, October 2007.Google Scholar
- L. Ceze et al. BulkSC: Bulk Enforcement of Sequential Consistency. In Proc. Intl. Symp. on Computer Architecture, 2007. Google ScholarDigital Library
- T. Elmas, S. Qadeer, and S. Tasiran. A race and transaction-aware java runtime. In Proc. Conf. on Programming Language Design and Implementation, pages 245--255, 2007. Google ScholarDigital Library
- K. Gharachorloo. Memory Consistency Models for Shared Memory Multiprocessors. PhD thesis, Stanford University, 1995. Google ScholarDigital Library
- K. Gharachorloo et al. Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. In Proc. 17th Intl. Symp. on Computer Architecture, pages 15--26, 1990. Google ScholarDigital Library
- K. Gharachorloo, A. Gupta, and J. Hennessy. Two Techniques to Enhance the Performance of Memory Consistency Models. In Proc. Intl. Conf. on Parallel Processing, pages I355--I364, 1991.Google Scholar
- W. H. Harrison. Compiler analysis of the value ranges for variables. IEEE Trans. Software Engineering, 3(3), May 1977. Google ScholarDigital Library
- IEEE and The Open Group. IEEE Standard 1003.1-2001. IEEE, 2001.Google Scholar
- Intel Corp. Intel 64 Architecture Memory Ordering White Paper, August 2007. http://www.intel.com/products/processor/manuals/318147.pdf.Google Scholar
- A. Kamil, J. Su, and K. Yelick. Making sequential consistency practical in titanium. In Proceedings of the 2005 ACM/IEEE SC|05 Conference (SC'05), page November, 2005. Google ScholarDigital Library
- L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9):690--691, 1979. Google ScholarDigital Library
- J. Manson, W. Pugh, and S. Adve. The Java memory model. In Proc. Symp. on Principles of Programming Languages, 2005. Google ScholarDigital Library
- S. Narayanasamy et al. Automatically classifying benign and harmful data races using replay analysis. In Proc. Conf. on Programming Language Design and Implementation, pages 22--31, 2007. Google ScholarDigital Library
- C. Nelson and H.-J. Boehm. Concurrency memory model (final revision). C++ standards committee paper WG21/N2429=J16/07-0299, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2429.htm, October 2007.Google Scholar
- P. Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proc. Symposium on Parallel Algorithms and Architectures, 1997. Google ScholarDigital Library
- D. Shasha and M. Snir. Efficient and correct execution of parallel programs that share memory. ACM Transactions on Programming Languages and Systems, 10(2):282--312, April 1988. Google ScholarDigital Library
- Z. Sura et al. Compiler Techniques for High Performance Sequentially Consistent Java Programs. In Symp. Principles and Practice of Parallel Programming, 2005. Google ScholarDigital Library
- H. Sutter. Prism: A principle-based sequential memory model for microsoft native code platforms. C++ standards committee paper WG21/N2197 = J16/07-0057, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2197.pdf, March 2007.Google Scholar
- United States Department of Defense. Reference Manual for the Ada Programming Language: ANSI/MIL-STD-1815A-1983 Standard 1003.1-2001, 1983. Springer. Google ScholarDigital Library
- T. Wenisch et al. Mechanisms for Store-wait-free Multiprocessors. In Proc. Intl. Symp. on Computer Architecture, 2007. Google ScholarDigital Library
Index Terms
- Foundations of the C++ concurrency memory model
Recommendations
Foundations of the C++ concurrency memory model
PLDI '08Currently multi-threaded C or C++ programs combine a single-threaded programming language with a separate threads library. This is not entirely sound [7].
We describe an effort, currently nearing completion, to address these issues by explicitly ...
Towards transactional memory semantics for C++
SPAA '09: Proceedings of the twenty-first annual symposium on Parallelism in algorithms and architecturesTransactional memory (TM) eliminates many problems associated with lock-based synchronization. Over recent years, much progress has been made in software and hardware implementation techniques for TM. However, before transactional memory can be ...
Assertional reasoning about data races in relaxed memory models
PPoPP '08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programmingWe describe the ideas behind a method to use assertional reasoning to statically show that all sequentially consistent executions of a concurrent program are free from data races.
Comments