ABSTRACT
Clock gating has become a standard practice for saving dynamic power in the clock network. Due to design reuse, it is common to find designs that have already some partial clock gating. We propose to exploit the existing clock gating in order to extract stronger gating conditions for blocks that are poorly gated or not gated at all. A second contribution of our paper is a robust and scalable approach to extract stability conditions for clock gating. Finally, we present a uniform treatment of unobservability and stability as dual approaches for propagating gating conditions forward and backward. Experimental results demonstrate significant power reduction (in the range of 14% -- 55% of the clock power) on Intel micro-processor designs.
- L. Benini and G. De Micheli. Automatic synthesis of low-power gated-clock finite-state machines, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 15(6), Jun. 1996 Google ScholarDigital Library
- V. Tiwari, S. Malik and P. Ashar. Guarded evaluation: Pushing power management to logic synthesis/design. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 17(10), Oct. 1998. Google ScholarDigital Library
- L Benini, G De Micheli, E Macii, M Poncino and R. Scarsi. Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. ACM Trans. on Design Automation of Electronic Systems, 4(4), 1999 Google ScholarDigital Library
- W. Qing, M. Pedram and W. Xunwei. Clock-gating and its application to low power design of sequential circuits. IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 47 (3), Mar. 2000Google Scholar
- P. Babighian, L. Benini and E. Macii. A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 24(1), Jan. 2005. Google ScholarDigital Library
- A. Hurst. Fast synthesis of clock gates from existing logic. International Workshop on Logic Synthesis (IWLS) 2007Google Scholar
- M. Damiani and G. De Micheli. Observability don't care sets and Boolean relations. Proc. of International Conference on Computer Aided Design (ICCAD) 1990Google Scholar
Index Terms
- A new paradigm for synthesis and propagation of clock gating conditions
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