John O'Leary
ABSTRACT
We used the Spin model checker to show that Intel's implementation of software transactional memory is correct, and built a preprocessor to accelerate the performance of Spin on parameterized models of shared-memory protocols.
- A. Adl-Tabatabai et al. Compiler and runtime support for efficient software transactional memory. In Proceedings of the ACM Conference on Programming Language Design and Implementation, pages 26--37, June 2006. Google Scholar
Digital Library
- R. Alur, K. McMillan, and D. Peled. Model-checking of correctness conditions for concurrent objects. In Proceedings of the IEEE Symposium on Logic in Computer Science, pages 219--228, July 1996. Google ScholarDigital Library
- A. Cohen, J. O'Leary, A. Pnueli, M. R. Tuttle, and L. Zuck. Verifying correctness of transactional memories. In M. Sheeran and J. Baumgartner, editors, Proceedings of the Symposium on Formal Methods in Computer Aided Design, pages 37--44, November 2007. Google ScholarDigital Library
- G. Holzman. The Spin Model Checker: Primer and Reference Manual. Addison-Wesley, 2004. Google ScholarDigital Library
Index Terms
- Model checking transactional memory with spin
Recommendations
Model Checking Transactional Memory with Spin
ICDCS '09: Proceedings of the 2009 29th IEEE International Conference on Distributed Computing SystemsWe used the Spin model checker to show that Intel's implementation of software transactional memory is correct. Transactional memory makes it possible to write properly-synchronized multi-threaded programs without the explicit use of locks. We describe ...
Implementing and Evaluating a Model Checker for Transactional Memory Systems
ICECCS '10: Proceedings of the 2010 15th IEEE International Conference on Engineering of Complex Computer SystemsTransactional Memory (TM) is a promising technique that addresses the difficulty of parallel programming. Since TM takes responsibility for all concurrency control, TM systems are highly vulnerable to subtle correctness errors. Due to the difficulty of ...
Transactional memory: from semantics to silicon
IWMSE '08: Proceedings of the 1st international workshop on Multicore software engineeringMulti-core architectures bring parallel programming into the mainstream. Parallel programming poses many new challenges to the developer, one of which is synchronizing concurrent access to shared memory by multiple threads. Programmers have ...
Comments