P. Bernardi
M. Sonza Reorda
ABSTRACT
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in order to guarantee high test quality, while minimizing application costs. Consequently, Low-Cost test strategies can be run on testers offering lower performance and/or reduced features with respect to traditional Automatic Test Equipments (ATEs); these equipments are usually referred to as Low-Cost testers.
This paper proposes a methodology for reducing the test data volume for the application of SoC Low-Cost test procedures. The method exploits a tester architecture organization suitable for SoCs testing, which includes a programmable device: the usage of this configurable block joined to the analysis of test pattern regularities permits minimizing the test data volume, thus improving the tester capabilities. The proposed method relies on test pattern compression at system level and it does not address core level pattern manipulation, as several other previously published works do.
Case studies are proposed, which provide data about the application of the proposed methodology to the test of SoCs including self-testable processor and memory cores. IEEE 1149.1 and IEEE 1500 test access mechanisms are considered. The achieved pattern depth reduction ratio is up to about the 64% for the considered case studies.
- P. T. Gonciari et al. "Integrated test data decompression and core wrapper design for low-cost system-on-a-chip testing" IEEE International Test Conference, 2002, page(s):64--73 Google Scholar
Digital Library
- Beck, M. et al. "Measures to improve delay fault testing on lowcost testers - a case study", IEEE VLSI Test Symposium, 2005, page(s):223--228 Google ScholarDigital Library
- Zorian, Y.; "Guest editor's introduction: what is infrastructure IP?", IEEE Design & Test of Computers, Volume 19, Issue 3, May-June 2002 Page(s):3--5 Google ScholarDigital Library
- M. Psarakis et al. "Systematic software-based self-test for pipelined processors", ACM/IEEE Design Automation Conference, 2006, page(s):393--398 Google ScholarDigital Library
- A. Benso et al. "HD2BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs", IEEE International Test Conference, 2000, page(s): 892--901 Google ScholarDigital Library
- Stroud, C. E.; "A designer's Guide to Built_In Self_Test", Kluwer Academic Publisher, 2002Google Scholar
- http://www.vsi.org/, 2006Google Scholar
- E. J. Marinissen et al. "Towards a standard for embedded core test: an example", IEEE International Test Conference, 1999, page(s): 696--705 Google ScholarDigital Library
- K. Chakrabarty, "Low-cost modular testing and test resource partitioning for SOCs", IEE Proceedings - Computers and Digital Techniques, Volume 152, Issue 3, 6 May 2005 Page(s):427--441Google ScholarCross Ref
- IEEE 1149.1--1990 Standard Test Access Port and Boundary-Scan architecture Google ScholarDigital Library
- D. Appello et al. "Exploiting programmable BIST for the diagnosis of embedded memory cores", IEEE International Test Conference, 2003, pp. 379--385Google Scholar
- E. J. Marinissen et al. "The role of test protocols in testing embedded-core-based system ICs", IEEE European Test Workshop 1999. Google ScholarDigital Library
Index Terms
- An novel methodology for reducing SoC test data volume on FPGA-based testers
Recommendations
Power-aware SoC test planning for effective utilization of port-scalable testers
Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which can ...
Test Integration for SOC Supporting Very Low-Cost Testers
ATS '09: Proceedings of the 2009 Asian Test SymposiumTo reduce test cost for SOC products, it is important to reduce the cost of testers. When using low-cost testers which have a limited test bandwidth to perform testing, Built-In- Self-Test (BIST) is necessary to reduce the data volume to be transmitted ...
REDUCING TEST DATA VOLUME USING EXTERNAL/LBIST HYBRID TEST PATTERNS
ITC '00: Proceedings of the 2000 IEEE International Test ConferenceA common approach for large industrial designs is touse logic built-in self-test (LBIST) followed by test datafrom an external tester. Because the fault coverage withLBIST alone is not sufficient, there is a need to top-up thefault coverage with ...
Comments