ABSTRACT
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized excess production. While only recently studied, IC piracy has now become a major challenge for the electronics and defense industries [6].
We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking algorithm, and (iii) innovative use of public-key cryptography. Our evaluation suggests that the overhead of EPIC on circuit delay and power is negligible, and the standard flows for verification and test do not require change. In fact, major required components have already been integrated into several chips in production. We also use formal methods to evaluate combinational locking and computational attacks. A comprehensive protocol analysis concludes that EPIC is surprisingly resistant to various piracy attempts.
- Y. Alkabani and F. Koushanfar. Active hardware metering for intellectual property protection and security. In USENIX Security, pp. 291--306, 2007. Google ScholarDigital Library
- Y. Alkabani, F. Koushanfar, and M. Potkonjak. Remote activation of ICs for piracy prevention and digital rights management. In IEEE/ACM ICCAD, pp. 674--677, 2007. Google ScholarDigital Library
- R. Anderson. Security Engineering: A guide to building dependable distributed systems. John Wiley and Sons, 2001. Google ScholarDigital Library
- F. Brglez and H. Fujiwara. A neutral netlist of 10 combinational circuits and a target translator in FORTRAN. In IEEE ISCAS, 1985.Google Scholar
- P. Clarke. Fake NEC company found, says report. EE Times, May 4, 2006. http://www.eetimes.com/showArticle.jhtml?articleID=187200176Google Scholar
- Defense Science Board (DSB) study on High Performance Microchip Supply. http://www.acq.osd.mil/dsb/reports/2005-02-HPMS_Report_Final.pdfGoogle Scholar
- N. Ferguson and B. Schneier. Practical Cryptography. John Wiley and Sons, 2003. Google ScholarDigital Library
- G. D. Hachtel and F. Somenzi. Logic Synthesis and Verification Algorithms. Kluwer, 2000 Google ScholarDigital Library
- F. Koushanfar, G. Qu, and M. Potkonjak. Intellectual property metering. In Inf. Hiding Workshop, pp. 81--95, 2001. Google ScholarDigital Library
- M. LaPedus, Qualcomm cracks top-10 in chip rankings. EE Times, August 23, 2007. http://www.eetimes.com/news/semi/showArticle.jhtml?articleID= 201801923Google Scholar
- K. Lofstrom, W. Daasch, and D. Taylor. IC identification circuits using device mismatch. In ISSCC, pp. 372--373, 2000.Google ScholarCross Ref
- C. Mouli and W. Carriker. Future fab. IEEE Spectrum 44(3), pp. 38--43, March 2007. http://www.spectrum.ieee.org/mar07/4941 Google ScholarDigital Library
- U. M. Nawathe et al. An 8-Core 64-thread 64b power-efficient SPARC SoC. In ISSCC, pp. 108--611, 2007. http://www.opensparc.net/opensparc-t2/index.htmlGoogle Scholar
- B. Santo, Plans for next-gen chips imperiled. IEEE Spectrum 44(8), pp. 12--14, August 2007.http://www.spectrum.ieee.org/aug07/5394 Google ScholarDigital Library
- Sciworx RSA Co-Processor. http://www.sci-worx.com/products/cryptography/rsa-co-processor.htmlGoogle Scholar
- F. Somenzi, CUDD: CU decision diagram package. ver. 2.4.1, Univ. of Colorado at Boulder, 2004. http://vlsi.colorado.edu/~fabio/CUDD/Google Scholar
- Y. Su, J. Holleman, and B. Otis. A 1.6J/bit stable chip ID generating circuit using process variations. In ISSCC, pp. 406--611, 2007.Google Scholar
- G. E. Suh and S. Devadas. Physical unclonable functions for device authentication and secret key generation. In DAC, pp. 9--14, 2007. Google ScholarDigital Library
- C. Tokunaga, D. Blaauw and T. Mudge. True random number generator with a metastability-based quality control. In IEEE ISSCC, pp. 404--405, 2007.Google ScholarCross Ref
- S. Trimberger. Trusted design in FPGAs. DAC "07, pp. 5--8. Google ScholarDigital Library
- VSI Alliance - IP Protection Development Working Group. The value and management of intellectual assets. 2000. http://vsi.org/documents/datasheets/TOC_IPPWP210.pdfGoogle Scholar
Index Terms
- EPIC: ending piracy of integrated circuits
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