David Y. Feinstein
ABSTRACT
This paper investigates partially redundant logic detection and gate modification coverage in both reversible and irreversible (classical) logic circuits. Our methodology is to repeatedly compare a benchmark circuit with a modified copy of itself using an equivalence checker. We have found many instances in the irreversible logic ISCAS85 benchmarks where single gate replacements were not detected, indicating no change in functionality after gate replacement. In contrast, we demonstrate that the Maslov reversible and quantum logic benchmarks exhibit very high gate modification fault coverage, in line with the expectation that reversible circuits, which implement bijective functions, have maximal information content.
- V. D. Agrawal, "An information theoretic approach to digital fault testing,", In IEEE Trans. Comp,. Vol. 30, pp. 582--587, 1981. Google Scholar
Digital Library
- R. E. Bryant. "Graph-Based Algorithms for Boolean Function Manipulation". In IEEE Trans. Comp, C-35(8):677--691, 1986. Google ScholarDigital Library
- D. Y. Feinstein, V. S. S. Nair, and M. A. Thornton, "Advances in Quantum Computing Fault Tolerance and Testing", In Proc of High Assurance System Engineering Symposium,. pp. 369--370, Nov. 2007. Google ScholarDigital Library
- C-Y. Huang, B. Yang, H-C Tsai and K-T Cheng, "Static Property Checking Using ATPG v.s. BDD Techniques", 2000 Proceeding of International Test Conference, pages 309--316. 2000. Google ScholarDigital Library
- D. Maslov. Reversible logic synthesis benchmarks page. Online: http://www.cs.uvic.ca/~dmaslov/, Nov. 15, 2005.Google Scholar
- D. M. Miller, D. Maslov, and G. W. Dueck. "A transformation based algorithm for reversible logic synthesis". In DAC'03, pp. 318--323, 2003. Google ScholarDigital Library
- D. M. Miller and M. A. Thornton, "QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits", In ISMVL'06, on CD, May 17--20, 2006. Google ScholarDigital Library
- D. M. Miller, D. Y. Feinstein, and M. A. Thornton, "QMDD Minimization using Sifting for Variable Reordering", In Journal of Multiple-valued Logic and Soft Computing. pp. 537--552., 2007.Google Scholar
- K. N. Patel, J. P. Hayes, and I. L. Markov, "Fault testing for reversible logic", In IEEE Trans. on CAD of IC and Systems, Vol. 23, No. 8, pp. 1220--1230, August 2004. Google ScholarDigital Library
- B. Ratchev, M. Hutton, G. Baeckler and B. van Antwerpen, "Logic synthesis and mapping: Verifying the correctness of FPGA logic synthesis algorithms", In Proc ACM/SIGDA 11th international symposium on Field programmable gate arrays, Feb. 2003 Google ScholarDigital Library
- F. Somenzi, "The CUDD Package", University of Colorado at Boulder, Version 3.2.1 available at: http://vlsi.colorado.edu/~fabio/.Google Scholar
Index Terms
- Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits
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