Love Singhal
ABSTRACT
Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development time, and potentially high performance under constraints and challenges driven by applications. An important design challenge at 45nm for multi-core system is manufacturing process variation. Due to increasing concern of WID variation, designers will have to choose configurations of processing cores that maximize yield of the system while not affecting performance and throughput constraints. Due to interdependency between processor configuration selection and task allocation and its impact on yield and latency constraints, we tackle both problems simultaneously. In this paper, we propose the problem of task allocation and configuration selection for yield optimization. We prove the problem is NP-hard and propose an optimal pseudo-polynomial on Serial-Parallel graphs. We target streaming applications in pipelined reconfigurable multiprocessor systems. We provide a case study of configurable Leon processors as the cores implemented on FPGA. Results show that proposed problem could result in significant improvement of the timing yield of the system by exploiting extra slack on tasks.
- C. Zhang, F. Vahid, and W. Najjar, "A highly configurable cache architecture for embedded systems," in Int. Symp. on Computer Architecture, 2003, pp. 136--146. Google Scholar
Digital Library
- L. Wehmeyer, M. K. Jain, S. Steinke, P. Marwedel, and M. Balakrishnan, "Analysis of the influence of register file size on energy consumption, code size, and execution time," IEEE Trans. Computer-Aided Design of Integrated Circuits, pp. 1329--1337, Nov. 2001. Google ScholarDigital Library
- J. Cong, G. Han, and W. Jiang, "Synthesis of an application-specific soft microprocessor system," in ACM FPGA 07, 2007. Google ScholarDigital Library
- F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors," in IEEE VLSID, 2005. Google ScholarDigital Library
- X. Liang and D. Brooks, "Mitigating the impact of process variations on processor register files and execution units," in MICRO, 2006, pp. 504--514. Google ScholarDigital Library
- F. Wang, X. Wu, and Y. Xie, "Variability-driven module selection with joint design time optimization and post-silicon tuning," in IEEE ASPDAC, 2008. Google ScholarDigital Library
- F. Weng, C. A. Nicopoulos, X. Wu, Y. Xie, and V. Narayanan, "Variation-aware task allocation and scheduling for mpsoc," in IEEE ICCAD, 2007. Google ScholarDigital Library
- J. Jung and T. Kim, "Timing variation-aware high-level synthesis," in IEEE ICCAD, 2007. Google ScholarDigital Library
- S. G. Duvall, "Statistical circuit modelling and optimizations," in Intl. Workshop Statistical Metrology, June 2000, pp. 56--63.Google Scholar
- P. Sedcole and P. Y. K. Cheung, "Parametric yield in fpgas due to within-die delay variations: A quantitative analysis," in ACM FPGA, 2007. Google ScholarDigital Library
- X. Liang and D. Brooks, "Microarchitecture parameter selection to optimize system performance under process variation," in IEEE ICCAD, 2006. Google ScholarDigital Library
- S. Ghiasi, K. Nguyen, E. Bozorgzadeh, and M. Sarrafzadeh, "On computation and resource management in networked embedded systems," in IPDPS, 2003.Google Scholar
- R. P. Dick, "Embedded systems synthesis benchmarks suite (e3s)." {Online}. Available: http://www.ece.northwestern.edu/ dickrp/e3sGoogle Scholar
- "Leon open-source processor." {Online}. Available: http://www.embedded-kernel-track.org/2004/papers.htmlGoogle Scholar
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