FPGA-based hardware acceleration for Boolean satisfiability

Reviewer: Javier Castillo

The Boolean satisfiability (SAT) problem is the most important nondeterministic polynomial time (NP) complete problem, since it is key to defining all of the other NP-complete problems. Since other NP-complete problems can be converted to SAT problems in a polynomial amount of time, a SAT solver-such as the one presented in this work-is able to solve not only the SAT problem, but any other NP-complete problem, such as the vertex cover problem, which is fundamental for optimization tasks. For this reason, this work is very relevant. The main contribution of the paper is a scalable SAT solver that is able to solve problems with up to 10K variables and 280K clauses. The system is implemented on a Virtex 2 Pro board-which is a bit old-and shows a 17 times speedup compared to a software approach. The paper also estimates the system's performance when running on a newer Virtex 4 field-programmable gate array (FPGA), but this test was not run on a real system. After presenting related work on SAT solvers, Gulati et al. introduce their system architecture. The paper is an adaptation of the previous work of one of the authors, where the same system was implemented on an application-specific integrated circuit (ASIC). In this FPGA version, the FPGA PowerPC processor is connected to the SAT engine; the PowerPC reads the problem instances from the board's double-data-rate synchronous dynamic random access memory (DDR SDRAM) and sends them to the engine, which collects and combines the results. Due to the length of the SAT problem solved, the authors divide it into smaller subproblems called bins; this is done by an external computer, using a heuristic algorithm. This is one of the major drawbacks of the work, because it renders the system unsuitable for embedded solutions. The transfer of data from the DDR to the SAT engine is not described, and this might be the bottleneck of the system; it might be possible to introduce a direct memory access (DMA) interface that speeds up the system. The authors do not provide information about the software running on the PowerPC processor; Does it run a standalone application or Linux__?__ Also, they do not describe the communication link between the host and the FPGA board; Is it RS232 or Ethernet__?__ To sum up, the architecture description is not complete; it should be extended in future papers. Section 4 presents the SAT engine algorithm. The system is able to solve the SAT problem by using a custom division into bins. The algorithm was used in a previous work and modified to fit the FPGA. The SAT engine tries to satisfy each bin, using stored global assignments. In brief, the algorithm begins by trying to satisfy the first bin; the resultant assignation goes to the next bin and tries to satisfy it. The algorithm continues until it finishes or finds an unsatisfiable bin. When a bin cannot be satisfied, it backtracks and tries another assignation to the variables. The partition into bins is done by using a bandwidth minimization algorithm that is presented in chapter 5. The experimental results show a 17 times speedup, compared to the MiniSAT algorithm running on a Pentium 4 machine, but these results are obtained using a set of formulas that extrapolate the performance from a Virtex 2 to a Virtex 4 FPGA. This performance model is not accurate, since one cannot compare the internal structure of the two FPGAs. It is clear that in a Virtex 4 board, the algorithm will run faster but the estimated performance may be incorrect for some cases. It shouldn't be too difficult to port the system to a Virtex 4 board and run the algorithm. Devoting 30 percent of the paper to justify the projection doesn't seem necessary; those pages could have been used to describe in detail the internal architecture of the system. Online Computing Reviews Service