K. Kunal
Abstract
This paper proposes a Hardware Transactional Memory (HTM) design for multi-core environments. Using a novel technique to keep track of transactional read-write entries, the design provides a holistic and scalable solution to Transactional Memory (TM) implementation issues of context switching, process migration and overflow handling. Another aspect of the design is that it allows transactions to run in a highly concurrent manner by using special techniques to handle conflict resolution, conflict detection and overflows. The feasibility and validity of the proposed design are demonstrated by developing a synthesizable Hardware Description Language (HDL) model of the design and also experimenting on the same with standard benchmarks.
- J. Bobba, N. Goyal, M.D. Hill, M.M. Swift, and D.A. Wood. Tokentm: Efficient execution of large transactions with hardware transactional memory. In Proc. of the 35th Annual Intl. Symp. on Computer Architecture, pages 127--138. Jun 2008. Google Scholar
Digital Library
- A. Shriraman, S. Dwarkadas, and M.L. Scott. Flexible decoupled transactional memory support. In Proc. of the 35th Annual Intl. Symp. on Computer Architecture, pages 139--150. Jun 2008. Google ScholarDigital Library
- L. Yen, J. Bobba, M.M. Marty, K.E. Moore, H. Volos, M.D. Hill, M.M. Swift, and D.A. Wood. Logtm-se: Decoupling hardware transactional memory from caches. In Proc. of the 13th Intl. Symp. on High-Performance Computer Architecture(HPCA), pages 261--272. Feb 2007. Google ScholarDigital Library
Index Terms
- HTM design spaces: complete decoupling from caches and achieving highly concurrent transactions
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