Ping Zhou
ABSTRACT
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high.
In this paper, we propose Early Write Termination (EWT), a novel technique to significantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED2. These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache.
- Y. Chen, X. Wang, H. Li, H. Liu, D. V. Dimitrov, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)," International Symposium on Quality Electronic Design, pp. 684--690, 2008. Google Scholar
Digital Library
- X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," Design Automation Conference, pp. 554--559, 2008. Google ScholarDigital Library
- M. Hosomi et.al. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM" IEEE International Electron Devices Meeting, pp. 459--462, 2005.Google Scholar
- D. H. Kang, et al., "Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology," IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 98--99, 2008.Google Scholar
- T. Kawahara et.al. "2 Mb SPRAM (SPin-Transfer Torque RAM) with Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read," IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, pp. 109--120, Jan. 2008.Google ScholarCross Ref
- S. Lai, T. Lowrey, "OUM - A 180nm Nonvolatile Memory Cell Element Technology for Standalone and Embedded Applications," International Electron Devices Meeting, pp. 36.5.1--36.5.4, 2001.Google Scholar
- B. C. Lee, E. Ipek, D. Burger "Architecting Phase Change Memory as a Scalable DRAM Alternative," to appear, International Symposium on Computer Architecture, 2009. Google ScholarDigital Library
- K. M. Lepak and M. H. Lipasti, "On the Value Locality of Store Instructions," International Symposium on Computer Architecture, pp. 182--191, 2000. Google ScholarDigital Library
- K. M. Lepak and M. H. Lipasti, "Silent Stores for Free," International Symposium on Microarchitecture, pp. 22--31, 2000. Google ScholarDigital Library
- J. Li, C. Augustine, S. Salahuddin, K. Roy, "Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Array for Yield Enhancement," Design Automation Conference, pp. 278--283, 2008. Google ScholarDigital Library
- P. S. Magnusson, et al., "Simics: A full system simulation platform," Computer, 35(2):50--58, 2002. Google ScholarDigital Library
- M. Hosomi, et al. "A Novel Nonvolatile Memory With Spin Torque Transfer Magnetization Switching: Spin-RAM," International Electron Devices Meeting, pp. 459--462, 2005.Google Scholar
- J. P. Singh, W. Weber, A. Gupta. "SPLASH: Stanford Parallel Applications for Shared-Memory". In Computer Architecture News, vol. 20, no. 1, pp 5--44. Google ScholarDigital Library
- G. Sun, X. Dong, Y. Xie, J. Li, Y. Chen, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs," The 15th International Symposium on High-Performance Computer Architecture, pp. 239--249, 2009.Google Scholar
- F. Tabrizi, "The Future of Scalable STT-RAM as a Universal Embedded Memory," Embedded.com, February 2007.Google Scholar
- S. Thoziyoor, N. Muralimanohar, J. H. Ahn, N. P. Jouppi, "CACTI 5.1", http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html, 2008.Google Scholar
- Y. Xie, G. H. Loh, B. Black, K. Bernstein, "Design space exploration for 3D architectures," ACM Journal on Emerging Technologies in Computing Systems (JETC), pp. 65--103, 2006. Google ScholarDigital Library
- F. Yeung, et al., "De
2
Sb
2
Te
5 Confined Structures and Integration of 64Mb Phase-Change Random Access Memory," Japanese Journal of Applied Physics, pp. 2691--2695, 2005.Google ScholarCross Ref
- "The International Technology Roadmap for Semiconductors, Process Integration, Device and Structures," http://www.itrs.net/links/2007itrs/2007_chapters/2007_PIDS.pdf 2007.Google Scholar
- P. Zhou, B. Zhao, J. Yang, Y. Zhang, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," The 36th International Symposium on Computer Architecture, To Appear, 2009. Google ScholarDigital Library
- J. G. Zhu, "Magnetoresistive Random AccessMemory: The Path to Competitiveness and Scalability," Proceedings of the IEEE, pp. 1786--1798, 2008.Google Scholar
- J. M. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits: A Design Perspective 2nd Edition," Prentice-Hall Electronics And VLSI Series, page 680--681, 2003. Google ScholarDigital Library
- K. Miura, et al., "A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion," Symposium on VLSI Technology Digest of Technical Papers, pp. 234--235, 2007.Google Scholar
- J. Hayakawa, et al., "Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers," IEEE Transactions on Magnetics, Vol. 44, No. 7, pp. 1962--1967, 2008.Google ScholarCross Ref
- M. Durlam, et al., "A 1-Mbit MRAM Based on 1T1MTJ Bit Cell Integrated With Copper Interconnects," IEEE Journal of Solid-State Circuits, Vol. 38, No. 5, pp. 769--773, 2003.Google ScholarCross Ref
- C. L. Su, et al., "Write Disturbance Modeling and Testing for MRAM," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 3, pp. 277--288, 2008. Google ScholarDigital Library
- D. Gogl, et al., "A 16-Mb MRAM Featuring Bootstrapped Write Drivers," IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, pp. 902--908, 2005.Google ScholarCross Ref
Index Terms
- Energy reduction for STT-RAM using early write termination
Recommendations
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique
Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density ...
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as cache ...
Endurance enhancement of write-optimized STT-RAM caches
MEMSYS '19: Proceedings of the International Symposium on Memory SystemsLow density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high ...
Comments