ShengYu Shen
ABSTRACT
One of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (E, E-1), in which circuit E transforms information into a format that is suitable for transmission and storage, while E's complementary circuit E-1 recovers this information.
In order to ease this job, we propose a novel two-step approach to synthesize complementary circuit E-1 from E fully automatically. First, we assume that the circuit E satisfies parameterized complementary assumption, which means its input can be recovered from its output under some parameter setting. We check this assumption with SAT solver and find out proper values of these parameters. Second, with parameter values and the SAT instance obtained in the first step, we build the complementary circuit E-1 with an efficient satisfying assignments enumeration technique that is specially designed for circuits with lots of XOR gates.
To illustrate its usefulness and efficiency, we run our algorithm on several complex encoders from industrial projects, including PCIE and 10G ethernet, and successfully generate correct complementary circuits for them.
- Chris Kozup. Is 802.11n Right for You? Mobility blog. 2008.Google Scholar
- Stephen J. Dubner. What Are the Lessons of the Blu-Ray/HD-DVD Battle? A Freakonomics Quorum. The New York Times. 2008.Google Scholar
- M. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In DAC'01, pp 530--535, 2001. Google ScholarDigital Library
- HoonSang Jin, Fabio Somenzi. Prime clauses for fast enumeration of satisfying assignments to boolean circuits. In DAC'05, pp 750--753, 2005. Google ScholarDigital Library
- K. L. McMillan. Applying SAT methods in unbounded symbolic model checking. In CAV'02, pp 250--264, 2002. Google ScholarDigital Library
- Kavita Ravi, Fabio Somenzi. Minimal Assignments for Bounded Model Checking. In TACAS'04, pp 31--45, 2004.Google Scholar
- H. Jin, H. Han, and F. Somenzi. Efficient conflict analysis for finding all satisfying assignments of a Boolean circuit. In TACAS'05, pp 287--300, 2005. Google ScholarDigital Library
- ShengYu Shen, Ying Qin, Sikun Li. Minimizing Counterexample with Unit Core Extraction and Incremental SAT. In VMCAI'05, pp 298--312, 2005. Google ScholarDigital Library
- Orna Grumberg, Assaf Schuster, Avi Yadgar. Memory Efficient All-Solutions SAT Solver and Its Application for Reachability Analysis. In FMCAD'04, pp 275--289, 2004.Google Scholar
- P. P. Chauhan, E. M. Clarke, and D. Kroening. A SAT-based algorithm for reparameterization in symbolic simulation. In DAC'04, pp 524--529, 2004. Google ScholarDigital Library
- IEEE Std. 802.3ae-2002. Amendment to IEEE Std 802.3-2002Google Scholar
- Alonzo Church. Logic, Arithmetic and Automata. International Congress of Mathematicians, pp 23--35, 1962Google Scholar
- J. R. Buchi and L. H. Landweber. Solving sequential conditions by finite-state strategies. Transaction American Mathematic Society, Vol 138:295--311, 1969.Google ScholarCross Ref
- M. O. Rabin. Automata on Infinite Objects and Church's Problem, volume 13 of Regional Conference Series in Mathematics. American Mathematic Society, 1972. Google ScholarDigital Library
- E. M. Clarke and E. A. Emerson. Design and synthesis of synchronization skeletons using branching time temporal logic. In IBM Workshop on Logics of Programs, LNCS 131, pp 52--71, 1981. Google ScholarDigital Library
- Z. Manna and P. Wolper. Synthesis of communicating processes from temporal logic specifications. ACM Trans. Prog. Lang. Sys., 6:68--93, 1984. Google ScholarDigital Library
- A. Pnueli and R. Rosner. On the synthesis of a reactive module. In Proc. 16th ACM Symp. Princ. of Prog. Lang., pages 179--190, 1989. Google ScholarDigital Library
- E. Asarin, O. Maler, A. Pnueli, and J. Sifakis. Controller synthesis for timed automata. In IFAC Symposium on System Structure and Control, pages 469--474. Elsevier, 1998.Google ScholarCross Ref
- R. Alur and S. La Torre. Deterministic generators and games for LTL fragments. ACM Trans. Comput. Log., 5(1):1--25, 2004. Google ScholarDigital Library
- N. Piterman, A. Pnueli and Y. Saar, Synthesis of Reactive(1) Designs, in VMCAI'06, pp 364--380, 2006. Google ScholarDigital Library
- S. Safra. Complexity of Automata on Infinite Objects. PhD thesis, The Weizmann Institute of Science, Rehovot, Israel, March 1989.Google Scholar
- Aidan Harding, Mark Ryan, and Pierre-Yves Schobbens. A New Algorithm for Strategy Synthesis in LTL Games. in TACAS'05, pp 477--492, 2005. Google ScholarDigital Library
- Oded Maler, Dejan Nickovic and Amir Pnueli. On Synthesizing Controllers from Bounded-Response Properties. In CAV'07, pp 95--107, 2007. Google ScholarDigital Library
- M. K. Ganai, A. Gupta, and P. Ashar. Efficient SAT-based unbounded symbolic model checking using circuit cofactoring. In ICCAD'04, pp 510--517, 2004. Google ScholarDigital Library
- Mealy, George H. A Method for Synthesizing Sequential Circuits. Bell Systems Technical Journal v 34, pp1045--1079, 1955.Google ScholarCross Ref
- E. J. McCluskey. Logic Design Principles. Prentice-Hall, 1986.Google Scholar
- O. Coudert. On solving covering problems. In DAC'96, 1996. Google ScholarDigital Library
- R. Rudell and A. Sangiovanni Vincentelli. Multiple valued minimization for PLA optimization. IEEE Transactions on CAD, 6(5), pp 727--750, 1987.Google ScholarDigital Library
- P. W. Besslich and M. Riege. An efficient program for logic synthesis of Mod-2 Sum Expressions. In Euro ASIC'91, pp 136--141, 1991.Google ScholarCross Ref
- T. Sasao. AND-EXOR expressions and their optimization. Kluwer Academic Publishers, Editor, Logic Synthesis and Optimization, Boston, 1993.Google ScholarCross Ref
- I. Reed. A class of multiple-error-correcting codes and their decoding scheme. IRETrans. on Inf. Theory, PGIT-4:48--49, 1954.Google Scholar
- M. Davio, Y. Deschamps, and A. Thayse. Discrete and switching Functions. George and McGraw-Hill, NY, 1978.Google Scholar
- A. Sarabi and M. Perkowski. Fast exact and quasi-minimal minimization of highly testable Fixed-Polarity AND/XOR canonical networks. In DAC'92, pp 30--35, 1992. Google ScholarDigital Library
- Rolf Drechsler, Bernd Becker, Michael Theobald. Fast OFDD based minimization of fixed polarity Reed-Muller expressions. in EURO-DAC, 1994. Google ScholarDigital Library
- Unni Narayanan and C. L. Liu. Low power logic synthesis for XOR based circuits. in ICCAD'97, pp 570--574, 1997. Google ScholarDigital Library
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- Synthesizing complementary circuits automatically
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